Repository navigation
docs: add ExternalSystemVerilogModule example to user guide #568 - #703
Open
AzazelSensei wants to merge 1 commit into
Open
AzazelSensei wants to merge 1 commit into
AzazelSensei wants to merge 1 commit into
Conversation
Add a wrapper example, generated instantiation, and notes on definitionName, parameters, and ports. Relates to intel#568.
Contributor
|
Thank you for your contribution! Will review as soon as I have a moment. |
There was a problem hiding this comment.
🟡 Changes recommended
The example fails for inputs whose width differs from the wrapper’s hard-coded default.
1 open finding
What changed in this PR
Adds an ExternalSystemVerilogModule example to the user guide.
Changes:
- Documents an external SystemVerilog module and Dart wrapper.
- Shows generated SystemVerilog and integration notes.
| File | Description |
|---|---|
doc/user_guide/_docs/A17-external-modules.md |
Adds the external-module example and guidance. |
🧠 Review effort: Balanced
💡 Add a code-review agent skill or configure MCP servers for context-aware, tailored reviews. Learn more in the docs.
| class TopModule extends Module { | ||
| TopModule(Logic a) { | ||
| a = addInput('a', a, width: a.width); | ||
| MyExternalModule(a); |
This branch has not been deployed
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Description & Motivation
The external modules user guide page had no example. I added a small wrapper around an existing SystemVerilog module, the generated instantiation, and notes on
definitionName, parameters, and ports.Related Issue(s)
Fixes #568
Testing
Docs-only. The Dart snippet matches the existing
test/external_test.dartwrapper (MyExternalModule/TopModule) and the generated instantiation that test already checks.Backwards-compatibility
No code change.
Documentation
This PR is the documentation update (
doc/user_guide/_docs/A17-external-modules.md).