Support VCDs generated by Verilator in VcdParser

.gitignore

@@ -22,4 +22,5 @@ tmp_test/
 # Exceptions
 !.vscode/extensions.json
 !test/example_icarus_waves.vcd
+!test/example_verilator_waves.vcd
 !test/sv_param_passthrough.sv

.pubignore

@@ -22,6 +22,7 @@ tmp_test/
 # Exceptions
 !.vscode/extensions.json
 !test/example_icarus_waves.vcd
+!test/example_verilator_waves.vcd
 !test/sv_param_passthrough.sv
 
 # Release with devtools build

lib/src/utilities/vcd_parser.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2025 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // vcd_parser.dart
@@ -49,8 +49,16 @@ abstract class VcdParser {
       } else if (state == _VcdParseState.findDumpVars) {
         if (line.contains(r'$dumpvars')) {
           state = _VcdParseState.findValue;
+          continue;
         }
-      } else if (state == _VcdParseState.findValue) {
+
+        if (line.startsWith('#')) {
+          // in case there's a missing $dumpvars section and jumps straight to #
+          state = _VcdParseState.findValue;
+        }
+      }
+
+      if (state == _VcdParseState.findValue) {
         if (line.startsWith('#')) {
           currentTime = int.parse(line.substring(1));
           if (currentTime > timestamp) {

test/example_verilator_waves.vcd

@@ -0,0 +1,115 @@
+$version Generated by VerilatedVcd $end
+$timescale 1ps $end
+ $scope module  $end
+  $scope module cosim_wrapper $end
+   $scope module external_module $end
+    $var wire 1 # clk $end
+    $var wire 1 $ push_valid $end
+    $var wire 8 % push_data [7:0] $end
+    $var wire 8 & sampled [7:0] $end
+   $upscope $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+0$
+b00000000 %
+b00000000 &
+#1
+#5000
+1#
+#5001
+1$
+#5002
+#10000
+0#
+#10001
+#15000
+1#
+#15001
+0$
+b00000001 %
+#15002
+#20000
+0#
+#20001
+#25000
+1#
+#25001
+1$
+b00000010 %
+#25002
+#30000
+0#
+#30001
+#35000
+1#
+b00000010 &
+#35001
+0$
+b00000011 %
+#35002
+#40000
+0#
+#40001
+#45000
+1#
+#45001
+1$
+b00000100 %
+#45002
+#50000
+0#
+#50001
+#55000
+1#
+b00000100 &
+#55001
+0$
+b00000101 %
+#55002
+#60000
+0#
+#60001
+#65000
+1#
+#65001
+1$
+b00000110 %
+#65002
+#70000
+0#
+#70001
+#75000
+1#
+b00000110 &
+#75001
+0$
+b00000111 %
+#75002
+#80000
+0#
+#80001
+#85000
+1#
+#85001
+1$
+b00001000 %
+#85002
+#90000
+0#
+#90001
+#95000
+1#
+b00001000 &
+#95001
+0$
+b00001001 %
+#95002
+#100000
+0#
+#100001
+#100002

test/vcd_parser_test.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2025 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // vcd_parser_test.dart
@@ -32,4 +32,22 @@ void main() {
       );
     }
   });
+
+  test('VCD parser can parse Verilator generated VCD file', () {
+    // NOTE: this one is extra interesting since initial values matter and it
+    // doesn't have a dumpvars section
+    final vcdContents =
+        File('test/example_verilator_waves.vcd').readAsStringSync();
+    for (var countI = 1; countI < 10; countI++) {
+      expect(
+        VcdParser.confirmValue(
+          vcdContents,
+          'sampled',
+          (10 * countI + 5) * 1000,
+          LogicValue.ofInt(countI.isEven ? countI - 2 : countI - 1, 8),
+        ),
+        isTrue,
+      );
+    }
+  });
 }