Skip to content

LogicNets, inOuts, and TriStateBuffer (support for bidirectional wires) #485

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 55 commits into from
Jun 4, 2024

Conversation

mkorbel1
Copy link
Contributor

@mkorbel1 mkorbel1 commented May 30, 2024

Description & Motivation

Support for bidirectional wires (LogicNets) and in-out ports (inOuts).

  • Added LogicNet
  • Added inOut ports to Module
  • Added TriStateBuffer
  • Deprecated CustomSytemVerilog and replaced with similar but more flexible APIs for SystemVerilog. BREAKING: This also impacted InlineSystemVerilog and ExternalSystemVerilogModule, whose APIs have changed.
  • Improved naming of intermediate, structure, and array signals in various places to make debug easier.
  • BREAKING: increased minimum Dart SDK to 3.0.0
  • BREAKING: updated Interface.connectIO API for inOutTags
  • Fixed a bug where expressionlessInputs may not have been honored in non-inline custom SystemVerilog modules.
  • Fixed a bug where in some cases an xor between two LogicValues could cause an exception due to a false width mismatch.
  • Added better checking, error handling, and message when module hierarchy cannot be properly resolved (e.g. self-containing modules, modules within multiple hierarchies).
  • Breaking: Updated APIs for Synthesizer.synthesize and down the stack to use a Function to calculate the instance type of a module instead of a Map look-up table.
  • Added srcConnections API to Logic to make it easier to trace drivers of subtypes of Logic which contain multiple drivers.

Related Issue(s)

Fix #8
Fix #476
Fix #477

Testing

Extensive new tests added for new features and bug fixes.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

Yes!

  • Breaking: ExternalSystemVerilogModule and InlineSystemVerilog now extend SystemVerilog instead of CustomSystemVerilog, meaning the instantiationVerilog API arguments have been modified.
  • Breaking: Increased minimum Dart SDK version to 3.0.0.
  • Breaking: Interface.connectIO has an additional optional named argument for inOutTags. Implementations of Interface which override connectIO will need to be updated.
  • Breaking: Updated APIs for Synthesizer.synthesize and down the stack to use a Function to calculate the instance type of a module instead of a Map look-up table.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Yes! Added to and updated user guide

@mkorbel1 mkorbel1 marked this pull request as ready for review May 31, 2024 18:21
@mkorbel1 mkorbel1 changed the title LogicNets and inOuts (support for bidirectional wires) LogicNets, inOuts, and TriStateBuffer (support for bidirectional wires) Jun 4, 2024
@mkorbel1 mkorbel1 merged commit b39abb2 into intel:main Jun 4, 2024
3 checks passed
@mkorbel1 mkorbel1 deleted the net branch June 4, 2024 18:08
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
1 participant