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LogicNet
s, inOut
s, and TriStateBuffer
(support for bidirectional wires)
#485
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LogicNet
s and inOut
s (support for bidirectional wires)LogicNet
s, inOut
s, and TriStateBuffer
(support for bidirectional wires)
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Description & Motivation
Support for bidirectional wires (
LogicNet
s) and in-out ports (inOut
s).LogicNet
inOut
ports toModule
TriStateBuffer
CustomSytemVerilog
and replaced with similar but more flexible APIs forSystemVerilog
. BREAKING: This also impactedInlineSystemVerilog
andExternalSystemVerilogModule
, whose APIs have changed.Interface.connectIO
API forinOutTags
expressionlessInputs
may not have been honored in non-inline custom SystemVerilog modules.xor
between twoLogicValue
s could cause an exception due to a false width mismatch.Synthesizer.synthesize
and down the stack to use aFunction
to calculate the instance type of a module instead of aMap
look-up table.srcConnections
API toLogic
to make it easier to trace drivers of subtypes ofLogic
which contain multiple drivers.Related Issue(s)
Fix #8
Fix #476
Fix #477
Testing
Extensive new tests added for new features and bug fixes.
Backwards-compatibility
Yes!
ExternalSystemVerilogModule
andInlineSystemVerilog
now extendSystemVerilog
instead ofCustomSystemVerilog
, meaning theinstantiationVerilog
API arguments have been modified.Interface.connectIO
has an additional optional named argument forinOutTags
. Implementations ofInterface
which overrideconnectIO
will need to be updated.Synthesizer.synthesize
and down the stack to use aFunction
to calculate the instance type of a module instead of aMap
look-up table.Documentation
Yes! Added to and updated user guide