An `If.block` with only one `Else` in it does not flag an error

[mkorbel1]

Describe the bug

If an If.block has only one Else with nothing else, it will simulate and generate without error, even though the generated verilog looks like this (note missing ()s).

ROHD:

    Combinational([
      If.block([
        Else([b < a])
      ])
    ]);

SystemVerilog:

//  combinational
always_comb begin
  if begin
      b = a;
  end 

end

To Reproduce

Construct a module such as this one:

class OnlyElseMod extends Module {
  OnlyElseMod(Logic a) {
    a = addInput('a', a);
    final b = addOutput('b');
    Combinational([
      If.block([
        Else([b < a])
      ])
    ]);
  }
}

Expected behavior

Raise exception

Actual behavior

No exception

Additional: Dart SDK info

No response

Additional: pubspec.yaml

No response

Additional: Context

No response