Create something like a `LogicStructure` to group `Logic`s in a way that can be used like `Logic`

[mkorbel1]

Is your feature request related to a problem? Please describe.
Similar to the ability to treat structs as signals in SystemVerilog.

Describe the solution you'd like
The LogicStructure object would extend Logic and could take a list of Logic in its constructor. These LogicStructures could then be used just like a Logic for assignments, conditional assignments, elements of interfaces, inputs/outputs of modules, etc.

The implementation of overridden Logic methods would simply loop through the collection of Logics.

Down the road, this could potentially map to a generated SystemVerilog struct or be used to implement arrays convertible to SystemVerilog.

Describe alternatives you've considered
An alternative is to just let each user individually determine a convenient way to group signals. Probably many users would implement it similarly and have a same set of base requirements.

[wswongat]

Does it also related to the multidimensional array?
The Logic class seems support 1D array only.
If I put them into a list, it will generate multiple logic variables instead of a single multidimensional array.
Am I understand correctly?

[mkorbel1]

Yes, I think this idea can be used to generate multi-dimensional arrays, but it will take some thought on how to implement things in a way that provides good value without overcomplicating things.

[mkorbel1]

This structuring or bundling should play nicely with Interfaces as well. For example, it would be nice to grab all of the signals in an Interface with a specific tag in one bundle, then assign those signals in another Interface.

This is also something that would be really useful for pipelining groups of signals using the Pipeline abstraction.

[mkorbel1]

There's desire to use this type of solution for at least wrapping/generating SystemVerilog modules with multi-dimensional ports