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81 changes: 78 additions & 3 deletions ADL/events/alderlake_goldencove_core.json
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.33",
"DatePublished": "07/03/2025",
"Version": "1.33",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.34",
"DatePublished": "08/29/2025",
"Version": "1.34",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -1732,6 +1732,31 @@
"PDISTCounter": "NA",
"Speculative": "1"
},
{
"EventCode": "0x2A,0x2B",
"UMask": "0x01",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"BriefDescription": "Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches.",
"PublicDescription": "Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "100003",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C4477",
"Precise": "0",
"CollectPEBSRecord": "0",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "1",
"Deprecated": "0",
"PDISTCounter": "0",
"Speculative": "0"
},
{
"EventCode": "0x2A,0x2B",
"UMask": "0x01",
Expand Down Expand Up @@ -1782,6 +1807,56 @@
"PDISTCounter": "0",
"Speculative": "0"
},
{
"EventCode": "0x2A,0x2B",
"UMask": "0x01",
"EventName": "OCR.COREWB_M.L3_HIT",
"BriefDescription": "Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches.",
"PublicDescription": "Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "100003",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C0008",
"Precise": "0",
"CollectPEBSRecord": "0",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "1",
"Deprecated": "0",
"PDISTCounter": "0",
"Speculative": "0"
},
{
"EventCode": "0x2A,0x2B",
"UMask": "0x01",
"EventName": "OCR.COREWB_NONM.L3_HIT",
"BriefDescription": "Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches.",
"PublicDescription": "Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches.",
"Counter": "0,1,2,3",
"PEBScounters": "0",
"SampleAfterValue": "100003",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1F803C1000",
"Precise": "0",
"CollectPEBSRecord": "0",
"TakenAlone": "0",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
"Data_LA": "0",
"L1_Hit_Indication": "0",
"Errata": "null",
"Offcore": "1",
"Deprecated": "0",
"PDISTCounter": "0",
"Speculative": "0"
},
{
"EventCode": "0x2A,0x2B",
"UMask": "0x01",
Expand Down
8 changes: 4 additions & 4 deletions ADL/events/alderlake_gracemont_core.json
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
{
"Header": {
"Copyright": "Copyright (c) 2001 - 2025 Intel Corporation. All rights reserved.",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.33",
"DatePublished": "07/03/2025",
"Version": "1.33",
"Info": "Performance Monitoring Events for 12th and 13th Generation Intel(R) Core(TM) Processor - V1.34",
"DatePublished": "08/29/2025",
"Version": "1.34",
"Legend": ""
},
"Events": [
Expand Down Expand Up @@ -3995,7 +3995,7 @@
"MSRValue": "0x00",
"Precise": "1",
"CollectPEBSRecord": "2",
"TakenAlone": "0",
"TakenAlone": "1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0",
Expand Down
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