Skip to content

Conversation

@akroviakov
Copy link
Contributor

This PR adds support for loading 1x16xf16 tiles by specifying the number of destination vector-registers (64B each) to be at least 1 (even for the cases when the actual payload is <64B).

@akroviakov akroviakov requested a review from Garra1980 August 30, 2024 13:00
@Garra1980 Garra1980 merged commit 5c647e7 into intel:main Aug 30, 2024
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants