[SYCL] Add new FPGA loop attribute enable_loop_pipelining #9263
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This patch adds support for new FPGA attribute called enable_loop_pipelining,
which is similar to disable_loop_pipelining.
This attribute is useful in the low-area flow, in which all loops are unpipelined
by default and the user may wish to enable loop pipelining.
The [[intel::enable_loop_pipelining]] attribute is applicable to loops in SYCL device code.
If the loop has this attribute, the LLVM IR loop will have the
llvm.loop.intel.pipelining.enable metadata, with value 1, as shown below:
br .... !llvm.loop !0
!0 = {!1}
!1 = !{!"llvm.loop.intel.pipelining.enable", i32 1}
An error should be output if both [[intel::enable_loop_pipelining]] and
[[intel::disable_loop_pipelining]] are applied to the same loop.
Signed-off-by: Soumi Manna <soumi.manna@intel.com>
premanandrao
reviewed
May 1, 2023
premanandrao
reviewed
May 2, 2023
Not a Problem @premanandrao. Thanks for catching and reviews! |
premanandrao
approved these changes
May 2, 2023
premanandrao
reviewed
May 2, 2023
elizabethandrews
approved these changes
May 2, 2023
|
Thank you everyone for reviews! |
|
The failed test is unrelated to my patch: Failed Tests (1): |
3 tasks
|
@intel/llvm-gatekeepers This PR is ready. Could you please merge it? Thank you |
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This patch adds support for new FPGA attribute called enable_loop_pipelining, which is similar to disable_loop_pipelining.
This attribute is useful in the low-area flow, in which all loops are unpipelined by default and the user may wish to enable loop pipelining.
The [[intel::enable_loop_pipelining]] attribute is applicable to loops in SYCL device code. If the loop has this attribute, the LLVM IR loop will have the llvm.loop.intel.pipelining.enable metadata, with value 1, as shown below:
br .... !llvm.loop !0
!0 = {!1}
!1 = !{!"llvm.loop.intel.pipelining.enable", i32 1}
An error should be output if both [[intel::enable_loop_pipelining]] and [[intel::disable_loop_pipelining]] are applied to the same loop.