Skip to content

[SYCL] Add vec assignment from scalar and more vec modulus overloads #9031

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Apr 28, 2023

Conversation

jzc
Copy link
Contributor

@jzc jzc commented Apr 11, 2023

vec now supports:

  • swizzle = scalar
  • swizzle % swizzle
  • swizzle % scalar
  • swizzle % vec
  • scalar % swizzle
  • scalar % vec

Fixes #8881 and #8877

Signed-off-by: Cai, Justin <justin.cai@intel.com>
@jzc jzc requested a review from a team as a code owner April 11, 2023 20:22
@jzc jzc requested a review from aelovikov-intel April 11, 2023 20:22
@jzc jzc temporarily deployed to aws April 11, 2023 21:58 — with GitHub Actions Inactive
@jzc jzc temporarily deployed to aws April 12, 2023 04:51 — with GitHub Actions Inactive
@jzc jzc temporarily deployed to aws April 14, 2023 18:12 — with GitHub Actions Inactive
@jzc jzc temporarily deployed to aws April 14, 2023 19:06 — with GitHub Actions Inactive
@jzc jzc temporarily deployed to aws April 20, 2023 15:58 — with GitHub Actions Inactive
@jzc jzc temporarily deployed to aws April 20, 2023 18:12 — with GitHub Actions Inactive
@AlexeySachkov AlexeySachkov merged commit 68e13d4 into intel:sycl Apr 28, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

operator% is not available for sycl::vec in some cases
3 participants