Skip to content

[clang][SYCL] Disable force inlining of kernel call operator for FGPA #8688

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
merged 1 commit into from
Mar 20, 2023
Merged

[clang][SYCL] Disable force inlining of kernel call operator for FGPA #8688

merged 1 commit into from
Mar 20, 2023

Conversation

Fznamznon
Copy link
Contributor

In some cases force inlining can remove necessary FPGA metadata. This happened with ivdep attribute attached to do .. while(1) loop.

@Fznamznon
[clang][SYCL] Disable force inlining kernel call operator for FGPA
7993717 
In some cases force inlining can remove necessary FPGA metadata. This
happened with `ivdep` attribute attached to `do .. while(1)` loop.
@Fznamznon Fznamznon requested review from a team as code owners March 17, 2023 13:03
smanna12
smanna12 approved these changes Mar 17, 2023
View reviewed changes
Copy link
Contributor

@smanna12 smanna12 left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thank you @Fznamznon

@Fznamznon Fznamznon temporarily deployed to aws March 17, 2023 13:42 — with GitHub Actions Inactive
@Fznamznon Fznamznon temporarily deployed to aws March 17, 2023 14:22 — with GitHub Actions Inactive
mdtoguchi
mdtoguchi approved these changes Mar 17, 2023
View reviewed changes
Copy link
Contributor

@mdtoguchi mdtoguchi left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM

@Fznamznon
Copy link
Contributor Author

ESIMD Emu LLVM Test Suite failure seem to be unrelated and fails for other PRs as well.

@bader bader mentioned this pull request Mar 17, 2023
Merged
@Fznamznon
Copy link
Contributor Author

@intel/llvm-gatekeepers , could you please merge this one? CI fail is unrelated.

@AlexeySachkov AlexeySachkov merged commit 90e0e65 into intel:sycl Mar 20, 2023
@steffenlarsen
Copy link
Contributor

@Fznamznon - It looks like CodeGenSYCL/fpga-attr-do-while-loops.cpp is failing on Windows in post-commit testing. Could you please investigate?

@Fznamznon
Copy link
Contributor Author

@Fznamznon - It looks like CodeGenSYCL/fpga-attr-do-while-loops.cpp is failing on Windows in post-commit testing. Could you please investigate?

Looking.

@Fznamznon
Copy link
Contributor Author

The fix for post commit is here #8710

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@premanandrao premanandrao premanandrao approved these changes

@mdtoguchi mdtoguchi mdtoguchi approved these changes

@elizabethandrews elizabethandrews elizabethandrews approved these changes

@smanna12 smanna12 smanna12 approved these changes

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
7 participants
@Fznamznon @steffenlarsen @premanandrao @mdtoguchi @elizabethandrews @smanna12 @AlexeySachkov