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[SYCL] Adds support for atomic fence capabilities device queries #8586
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[SYCL] Adds support for atomic fence capabilities device queries #8586
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Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
…fence_capabilities
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
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PI CUDA and PI HIP changes LGTM
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
sycl/source/detail/device_info.hpp
Outdated
info::device::atomic_fence_order_capabilities> { | ||
static std::vector<memory_order> get(RT::PiDevice dev, const plugin &Plugin) { | ||
pi_memory_order_capabilities result; | ||
Plugin.call_nocheck<PiApiKind::piDeviceGetInfo>( |
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Why nocheck
? Where do we perform error handling?
@@ -1025,13 +1051,27 @@ get_device_info_host<info::device::atomic_memory_order_capabilities>() { | |||
memory_order::acq_rel, memory_order::seq_cst}; | |||
} | |||
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template <> | |||
inline std::vector<memory_order> | |||
get_device_info_host<info::device::atomic_fence_order_capabilities>() { |
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I wonder when we will be able to stop specializing that for host device, because it doesn't really exists anymore
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
/testwin |
/verify with intel/llvm-test-suite#1658 |
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
…fence_capabilities
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
/testwin |
/verify with intel/llvm-test-suite#1658 |
@jchlanda @npmiller Sorry to bother you again, but I had to update HIP backend again. Atomic ref tests were failing because they use some of the queries we are updating here. We initially went for reporting an error because the queries went unsupported but that was causing mentioned tests to fail. Now, I'm just returning minimum mandated capabilities specified by SYCL 2020 while we wait for a final implementation for these queries in the backend (I'll open an issue to keep track). Please, check if everything makes sense to you. |
Friendly ping @intel/llvm-reviewers-runtime. |
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+1 on UR/L0 related changes.
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LGTM!
…el#8586) Adds support to query devices for `atomic_fence_order_capabilities` and `atomic_fence_scope_capabilities`. The backends supported are OpenCL and Level Zero. For the rest of backends, it has been left unsupported. Fixes intel#8293. --------- Signed-off-by: Maronas, Marcos <marcos.maronas@intel.com>
Adds support to query devices for
atomic_fence_order_capabilities
andatomic_fence_scope_capabilities
. The backends supported are OpenCL and Level Zero. For the rest of backends, it has been left unsupported.Fixes #8293.