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[LIBCLC] Fix atomic stores for NVPTX #7780

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Merged
merged 1 commit into from
Dec 14, 2022
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[LIBCLC] Fix atomic stores for NVPTX #7780

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12 changes: 6 additions & 6 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_store.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,11 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
}

#define __CLC_NVVM_ATOMIC_STORE_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, ADDR_SPACE, \
TYPE, TYPE_MANGLED, SUBSTITUTION, TYPE_NV, TYPE_MANGLED_NV, ADDR_SPACE, \
POINTER_AND_ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
__attribute__((always_inline)) _CLC_DECL void _Z19__spirv_\
AtomicStore##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagEN\
S1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
S##SUBSTITUTION##_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Expand Down Expand Up @@ -74,12 +74,12 @@ Memory order is stored in the lowest 5 bits */ \
}

#define __CLC_NVVM_ATOMIC_STORE(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV) \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, 1, TYPE_NV, TYPE_MANGLED_NV,\
__global, PU3AS1, _global_) \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, 1, TYPE_NV, TYPE_MANGLED_NV,\
__local, PU3AS3, _shared_) \
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, , \
P, _gen_)
__CLC_NVVM_ATOMIC_STORE_IMPL(TYPE, TYPE_MANGLED, 0, TYPE_NV, TYPE_MANGLED_NV,\
, P, _gen_)

__CLC_NVVM_ATOMIC_STORE(int, i, int, i)
__CLC_NVVM_ATOMIC_STORE(uint, j, int, i)
Expand Down