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Merged
merged 3 commits into from
Dec 14, 2022
Merged

[LIBCLC] Add support for more generic atomic operations #7391

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e1eeb3d
[LIBCLC] Add support for more generic atomic operations
jchlanda Oct 31, 2022
d2eb42f
Update libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl
jchlanda Dec 13, 2022
b35194f
Update libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl
jchlanda Dec 13, 2022
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111 changes: 59 additions & 52 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_cmpxchg.cl
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Original file line number Diff line number Diff line change
Expand Up @@ -69,63 +69,70 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_MemoryBarrier(unsigned int, unsigned int);
} \
}

#define __CLC_NVVM_ATOMIC_CAS_IMPL( \
TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, OP_MANGLED, ADDR_SPACE, \
ADDR_SPACE_MANGLED, ADDR_SPACE_NV) \
_CLC_DECL TYPE \
_Z29__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_MANGLED##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics1, \
enum MemorySemanticsMask semantics2, TYPE cmp, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = (semantics1 | semantics2) & 0x1F; \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ACQUIRE_FENCE( \
TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_CAS_IMPL_ACQUIRE_FENCE( \
TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
// Type __spirv_AtomicCompareExchange(AS Type *P, __spv::Scope::Flag S,
// __spv::MemorySemanticsMask::Flag E,
// __spv::MemorySemanticsMask::Flag U,
// Type V, Type C);
#define __CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, \
TYPE_MANGLED_NV, OP, OP_MANGLED, \
ADDR_SPACE, POINTER_AND_ADDR_SPACE_MANGLED, \
ADDR_SPACE_NV, SUBSTITUTION1, SUBSTITUTION2) \
__attribute__((always_inline)) _CLC_DECL TYPE _Z29__spirv_\
Atomic##OP_MANGLED##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5\
__spv5Scope4FlagENS##SUBSTITUTION1##_19Memory\
SemanticsMask4FlagES##SUBSTITUTION2##_##TYPE_MANGLED##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics1, \
enum MemorySemanticsMask semantics2, TYPE cmp, TYPE value) { \
/* Semantics mask may include memory order, storage class and other info \
Memory order is stored in the lowest 5 bits */ \
unsigned int order = (semantics1 | semantics2) & 0x1F; \
switch (order) { \
case None: \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
case Acquire: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acquire) \
} else { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ACQUIRE_FENCE( \
TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
case Release: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _release) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, ) \
} \
break; \
case AcquireRelease: \
if (__clc_nvvm_reflect_arch() >= 700) { \
__CLC_NVVM_ATOMIC_CAS_IMPL_ORDER(TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, \
ADDR_SPACE, ADDR_SPACE_NV, _acq_rel) \
} else { \
__spirv_MemoryBarrier(scope, Release); \
__CLC_NVVM_ATOMIC_CAS_IMPL_ACQUIRE_FENCE( \
TYPE, TYPE_NV, TYPE_MANGLED_NV, OP, ADDR_SPACE, ADDR_SPACE_NV) \
} \
break; \
} \
__builtin_trap(); \
__builtin_unreachable(); \
}

#define __CLC_NVVM_ATOMIC_CAS(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, OP_MANGLED) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
OP_MANGLED, __global, AS1, _global_) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, \
OP, OP_MANGLED, __local, AS3, _shared_)
OP_MANGLED, __global, PU3AS1, _global_, 1, 5) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
OP_MANGLED, __local, PU3AS3, _shared_, 1, 5) \
__CLC_NVVM_ATOMIC_CAS_IMPL(TYPE, TYPE_MANGLED, TYPE_NV, TYPE_MANGLED_NV, OP, \
OP_MANGLED, , P, _gen_, 0, 4)

__CLC_NVVM_ATOMIC_CAS(int, i, int, i, cas, CompareExchange)
__CLC_NVVM_ATOMIC_CAS(long, l, long, l, cas, CompareExchange)
Expand Down
34 changes: 19 additions & 15 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_inc_dec_helpers.h
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Original file line number Diff line number Diff line change
Expand Up @@ -12,25 +12,29 @@
#include <spirv/spirv.h>
#include <spirv/spirv_types.h>

#define __CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, \
ADDR_SPACE, ADDR_SPACE_MANGLED) \
TYPE \
_Z21__spirv_AtomicIAddEXTPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *, enum Scope, enum MemorySemanticsMask, \
TYPE); \
_CLC_DECL TYPE \
_Z24__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics) { \
return _Z21__spirv_AtomicIAddEXTPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
pointer, scope, semantics, VAL); \
#define __CLC_NVVM_ATOMIC_INCDEC_IMPL( \
TYPE, TYPE_MANGLED, OP_MANGLED, VAL, ADDR_SPACE, \
POINTER_AND_ADDR_SPACE_MANGLED, SUBSTITUTION) \
TYPE _Z21__spirv_\
AtomicIAddEXT##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv\
5Scope4FlagENS##SUBSTITUTION##_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *, enum Scope, enum MemorySemanticsMask, TYPE); \
__attribute__((always_inline)) _CLC_DECL TYPE _Z24__spirv_\
Atomic##OP_MANGLED##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv\
5Scope4FlagENS##SUBSTITUTION##_19MemorySemanticsMask4FlagE( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics) { \
return _Z21__spirv_\
AtomicIAddEXT##POINTER_AND_ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv\
5Scope4FlagENS##SUBSTITUTION##_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
pointer, scope, semantics, VAL); \
}

#define __CLC_NVVM_ATOMIC_INCDEC(TYPE, TYPE_MANGLED, OP_MANGLED, VAL) \
__attribute__((always_inline)) \
__CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, __global, \
AS1) __attribute__((always_inline)) \
PU3AS1, 1) \
__CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, __local, \
AS3)
PU3AS3, 1) \
__CLC_NVVM_ATOMIC_INCDEC_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, VAL, , P, 0)

#endif
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