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[SYCL][libdevice] Add type cast functions between half and float/integral type #6930

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Merged
merged 11 commits into from
Oct 26, 2022
Merged

[SYCL][libdevice] Add type cast functions between half and float/integral type #6930

merged 11 commits into from
Oct 26, 2022

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jinge90
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@jinge90 jinge90 commented Oct 1, 2022

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add fp2half
498f628 
Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90
Merge remote-tracking branch 'upstream/sycl' into FP32_64_to_half
1b87190
@jinge90
enable __imf_float2half_* in libdevice
ed6b1ff 
Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90 jinge90 requested review from a team as code owners October 1, 2022 03:48
@jinge90 jinge90 requested a review from dm-vodopyanov October 1, 2022 03:48
@jinge90 jinge90 marked this pull request as draft October 1, 2022 03:48
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[SYCL][libdevice] Add type cast util functions between half-precision…
55764e2 
… and float, integeral type

Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90 jinge90 mentioned this pull request Oct 2, 2022
Merged
jinge90 added 5 commits October 2, 2022 20:27
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fix bug of comparison between signed and unsigned value
21f5dd6 
Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90
add exp bias after exp adjustment
64b658f 
Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90
conforms to IEEE-754 standars for int2half conversion when overflow h…
09656e8 
…appens

Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90
fix bug in int2half overflow handing in RTP mode
c0f03c0 
Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90
Add double2half
1b6394f 
Signed-off-by: jinge90 <ge.jin@intel.com>
@jinge90 jinge90 marked this pull request as ready for review October 8, 2022 00:42
xtian-github
xtian-github approved these changes Oct 9, 2022
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LGTM

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jinge90 commented Oct 12, 2022

Hi, @intel/dpcpp-tools-reviewers
Could you take a look at this PR?
Thanks very much.

@jinge90 jinge90 requested a review from pvchupin October 14, 2022 04:00
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jinge90 commented Oct 14, 2022

Hi, @pvchupin
Could you take a look at this PR?

Thanks very much.

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jinge90 commented Oct 20, 2022

Hi, @pvchupin
Kind ping.

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@jinge90, please get @intel/dpcpp-tools-reviewers approval.

asudarsa
asudarsa reviewed Oct 20, 2022
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@jinge90 jinge90 requested a review from asudarsa October 24, 2022 03:20
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jinge90 commented Oct 26, 2022

Hi, @asudarsa and @pvchupin
Kind ping~

asudarsa
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Other than my earlier comment which has been resolved, the change looks good to me. Thanks

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jinge90 commented Oct 26, 2022

Hi, @pvchupin
Could you take a look if we can merge this patch?

Thanks very much.

@pvchupin pvchupin merged commit 599b1b9 into intel:sycl Oct 26, 2022
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@dm-vodopyanov dm-vodopyanov dm-vodopyanov approved these changes

@akolesov-nv akolesov-nv akolesov-nv approved these changes

@xtian-github xtian-github xtian-github approved these changes

@asudarsa asudarsa asudarsa approved these changes

@zettai-reido zettai-reido Awaiting requested review from zettai-reido

@pvchupin pvchupin Awaiting requested review from pvchupin

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@jinge90 @pvchupin @dm-vodopyanov @akolesov-nv @xtian-github @asudarsa