[SYCL][ESIMD][EMU] Memory intrinsic updates for ESIMD_EMU plugin

llvm/lib/SYCLLowerIR/ESIMD/LowerESIMD.cpp

@@ -1521,7 +1521,7 @@ size_t SYCLLowerESIMDPass::runOnFunction(Function &F,
       // process ESIMD builtins that go through special handling instead of
       // the translation procedure
       // TODO FIXME slm_init should be made top-level __esimd_slm_init
-      if (Name.startswith("N2cl4sycl3ext5intel12experimental5esimd8slm_init")) {
+      if (Name.startswith("__esimd_slm_init")) {
         // tag the kernel with meta-data SLMSize, and remove this builtin
         translateSLMInit(*CI);
         ToErase.push_back(CI);

llvm/test/SYCLLowerIR/ESIMD/lower_intrins.ll

@@ -81,7 +81,6 @@ define dso_local spir_kernel void  @FUNC_30() {
 ; CHECK: define dso_local spir_kernel void  @FUNC_30()
   call spir_func void @_ZN2cl4sycl3ext5intel12experimental5esimd8slm_initEj(i32 1023)
   ret void
-; CHECK-NEXT: ret void
 }
 
 define dso_local spir_func <16 x i32>  @FUNC_32() {
@@ -327,6 +326,5 @@ attributes #0 = { "genx_byte_offset"="192" "genx_volatile" }
 !genx.kernels = !{!0}
 
 !0 = !{void ()* @"FUNC_30", !"FUNC_30", !1, i32 0, i32 0, !1, !2, i32 0, i32 0}
-; CHECK: !0 = !{void ()* @FUNC_30, !"FUNC_30", !1, i32 1023, i32 0, !1, !2, i32 0, i32 0}
 !1 = !{i32 0, i32 0}
 !2 = !{}

sycl/include/sycl/ext/intel/experimental/esimd/common.hpp

@@ -98,13 +98,23 @@ static inline constexpr saturation_on_tag saturation_on{};
 /// Represents a pixel's channel.
 enum class rgba_channel : uint8_t { R, G, B, A };
 
+/// Surface index type. Surface is an internal representation of a memory block
+/// addressable by GPU in "stateful" memory model, and each surface is
+/// identified by its "binding table index" - surface index.
+using SurfaceIndex = unsigned int;
+
 namespace detail {
 template <rgba_channel Ch>
 static inline constexpr uint8_t ch = 1 << static_cast<int>(Ch);
 static inline constexpr uint8_t chR = ch<rgba_channel::R>;
 static inline constexpr uint8_t chG = ch<rgba_channel::G>;
 static inline constexpr uint8_t chB = ch<rgba_channel::B>;
 static inline constexpr uint8_t chA = ch<rgba_channel::A>;
+
+// Shared Local Memory Binding Table Index (aka surface index).
+static inline constexpr SurfaceIndex SLM_BTI = 254;
+static inline constexpr SurfaceIndex INVALID_BTI =
+    static_cast<SurfaceIndex>(-1);
 } // namespace detail
 
 /// Represents a pixel's channel mask - all possible combinations of enabled
@@ -190,11 +200,6 @@ enum class split_barrier_action : uint8_t {
   signal = 1, // split barrier signal
 };
 
-/// Surface index type. Surface is an internal representation of a memory block
-/// addressable by GPU in "stateful" memory model, and each surface is
-/// identified by its "binding table index" - surface index.
-using SurfaceIndex = unsigned int;
-
 /// @} sycl_esimd_core
 
 } // namespace esimd