[SYCL][FPGA] Rework blocking pipes

llvm-spirv/lib/SPIRV/OCLUtil.cpp

@@ -531,6 +531,15 @@ class OCLBuiltinFuncMangleInfo : public SPIRV::BuiltinFuncMangleInfo {
       addVoidPtrArg(1);
       addUnsignedArg(2);
       addUnsignedArg(3);
+      // OpenCL-like representation of blocking pipes
+    } else if (UnmangledName == "read_pipe_bl_2" ||
+               UnmangledName == "write_pipe_bl_2") {
+      // with 2 arguments (plus two i32 literals):
+      // int read_pipe_bl (read_only pipe gentype p, gentype *ptr)
+      // int write_pipe_bl (write_only pipe gentype p, const gentype *ptr)
+      addVoidPtrArg(1);
+      addUnsignedArg(2);
+      addUnsignedArg(3);
     } else if (UnmangledName == "read_pipe_4" ||
                UnmangledName == "write_pipe_4") {
       // with 4 arguments (plus two i32 literals):
@@ -655,6 +664,7 @@ bool isSamplerTy(Type *Ty) {
 
 bool isPipeBI(const StringRef MangledName) {
   return MangledName == "write_pipe_2" || MangledName == "read_pipe_2" ||
+         MangledName == "write_pipe_bl_2" || MangledName == "read_pipe_bl_2" ||
          MangledName == "write_pipe_4" || MangledName == "read_pipe_4" ||
          MangledName == "reserve_write_pipe" ||
          MangledName == "reserve_read_pipe" ||

llvm-spirv/lib/SPIRV/OCLUtil.h

@@ -183,6 +183,7 @@ const static char NDRangePrefix[] = "ndrange_";
 const static char Pipe[] = "pipe";
 const static char ReadImage[] = "read_image";
 const static char ReadPipe[] = "read_pipe";
+const static char ReadPipeBlockingINTEL[] = "read_pipe_bl";
 const static char RoundingPrefix[] = "_r";
 const static char Sampled[] = "sampled_";
 const static char SampledReadImage[] = "sampled_read_image";
@@ -204,6 +205,7 @@ const static char WaitGroupEvent[] = "wait_group_events";
 const static char WriteImage[] = "write_image";
 const static char WorkGroupBarrier[] = "work_group_barrier";
 const static char WritePipe[] = "write_pipe";
+const static char WritePipeBlockingINTEL[] = "write_pipe_bl";
 const static char WorkGroupPrefix[] = "work_group_";
 const static char WorkGroupAll[] = "work_group_all";
 const static char WorkGroupAny[] = "work_group_any";
@@ -603,6 +605,8 @@ template <> inline void SPIRVMap<std::string, Op, SPIRVInstruction>::init() {
   // CL 2.0 pipe builtins
   _SPIRV_OP(read_pipe_2, ReadPipe)
   _SPIRV_OP(write_pipe_2, WritePipe)
+  _SPIRV_OP(read_pipe_bl_2, ReadPipeBlockingINTEL)
+  _SPIRV_OP(write_pipe_bl_2, WritePipeBlockingINTEL)
   _SPIRV_OP(read_pipe_4, ReservedReadPipe)
   _SPIRV_OP(write_pipe_4, ReservedWritePipe)
   _SPIRV_OP(reserve_read_pipe, ReserveReadPipePackets)

llvm-spirv/lib/SPIRV/SPIRVToOCL20.cpp

@@ -467,7 +467,8 @@ void SPIRVToOCL20::visitCallSPIRVPipeBuiltin(CallInst *CI, Op OC) {
           Args.erase(Args.begin(), Args.begin() + 1);
 
         if (!(OC == OpReadPipe || OC == OpWritePipe ||
-              OC == OpReservedReadPipe || OC == OpReservedWritePipe))
+              OC == OpReservedReadPipe || OC == OpReservedWritePipe ||
+              OC == OpReadPipeBlockingINTEL || OC == OpWritePipeBlockingINTEL))
           return DemangledName;
 
         auto &P = Args[Args.size() - 3];

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

@@ -114,13 +114,15 @@ typedef spv::Dim SPIRVImageDimKind;
 typedef std::vector<SPIRVCapabilityKind> SPIRVCapVec;
 
 enum SPIRVExtensionKind {
+  SPV_INTEL_blocking_pipes,
   SPV_INTEL_device_side_avc_motion_estimation,
   SPV_KHR_no_integer_wrap_decoration
 };
 
 typedef std::set<SPIRVExtensionKind> SPIRVExtSet;
 
 template <> inline void SPIRVMap<SPIRVExtensionKind, std::string>::init() {
+  add(SPV_INTEL_blocking_pipes, "SPV_INTEL_blocking_pipes");
   add(SPV_INTEL_device_side_avc_motion_estimation,
       "SPV_INTEL_device_side_avc_motion_estimation");
   add(SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration");
@@ -156,6 +158,7 @@ template <> inline void SPIRVMap<SPIRVCapabilityKind, SPIRVCapVec>::init() {
   ADD_VEC_INIT(CapabilityImageReadWrite, {CapabilityImageBasic});
   ADD_VEC_INIT(CapabilityImageMipmap, {CapabilityImageBasic});
   ADD_VEC_INIT(CapabilityPipes, {CapabilityKernel});
+  ADD_VEC_INIT(CapabilityBlockingPipesINTEL, {CapabilityKernel});
   ADD_VEC_INIT(CapabilityDeviceEnqueue, {CapabilityKernel});
   ADD_VEC_INIT(CapabilityLiteralSampler, {CapabilityKernel});
   ADD_VEC_INIT(CapabilityAtomicStorage, {CapabilityShader});

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h

@@ -2092,6 +2092,24 @@ _SPIRV_OP(GroupCommitReadPipe, false, 6)
 _SPIRV_OP(GroupCommitWritePipe, false, 6)
 #undef _SPIRV_OP
 
+class SPIRVBlockingPipesIntelInst : public SPIRVInstTemplateBase {
+protected:
+  SPIRVCapVec getRequiredCapability() const override {
+    return getVec(CapabilityBlockingPipesINTEL);
+  }
+
+  SPIRVExtSet getRequiredExtensions() const override {
+    return getSet(SPV_INTEL_blocking_pipes);
+  }
+};
+
+#define _SPIRV_OP(x, ...)                                                      \
+  typedef SPIRVInstTemplate<SPIRVBlockingPipesIntelInst, Op##x, __VA_ARGS__>   \
+      SPIRV##x;
+_SPIRV_OP(ReadPipeBlockingINTEL, true, 7)
+_SPIRV_OP(WritePipeBlockingINTEL, true, 7)
+#undef _SPIRV_OP
+
 class SPIRVAtomicInstBase : public SPIRVInstTemplateBase {
 public:
   SPIRVCapVec getRequiredCapability() const override {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h

@@ -558,6 +558,7 @@ inline bool isValid(spv::Capability V) {
   case CapabilityPipeStorage:
   case CapabilityFPGAMemoryAttributesINTEL:
   case CapabilityFPGALoopControlsINTEL:
+  case CapabilityBlockingPipesINTEL:
     return true;
   default:
     return false;
@@ -817,6 +818,8 @@ inline bool isValid(spv::Op V) {
   case OpGroupSMax:
   case OpReadPipe:
   case OpWritePipe:
+  case OpReadPipeBlockingINTEL:
+  case OpWritePipeBlockingINTEL:
   case OpReservedReadPipe:
   case OpReservedWritePipe:
   case OpReserveReadPipePackets:

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

@@ -486,6 +486,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
       "SubgroupAvcMotionEstimationChromaINTEL");
   add(CapabilityFPGAMemoryAttributesINTEL, "FPGAMemoryAttributesINTEL");
   add(CapabilityFPGALoopControlsINTEL, "FPGALoopControlsINTEL");
+  add(CapabilityBlockingPipesINTEL, "BlockingPipesINTEL");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCode.h

@@ -137,7 +137,8 @@ inline bool isGroupOpCode(Op OpCode) {
 
 inline bool isPipeOpCode(Op OpCode) {
   unsigned OC = OpCode;
-  return OpReadPipe <= OC && OC <= OpGroupCommitWritePipe;
+  return (OpReadPipe <= OC && OC <= OpGroupCommitWritePipe) ||
+         (OpReadPipeBlockingINTEL <= OC && OC <= OpWritePipeBlockingINTEL);
 }
 
 inline bool isSubgroupAvcINTELTypeOpCode(Op OpCode) {

llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h

@@ -429,3 +429,5 @@ _SPIRV_OP(SubgroupAvcSicGetIpeChromaModeINTEL, 5813)
 _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL, 5814)
 _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL, 5815)
 _SPIRV_OP(SubgroupAvcSicGetInterRawSadsINTEL, 5816)
+_SPIRV_OP(ReadPipeBlockingINTEL, 5946)
+_SPIRV_OP(WritePipeBlockingINTEL, 5947)

llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp

@@ -677,6 +677,7 @@ enum Capability {
   CapabilitySubgroupAvcMotionEstimationChromaINTEL = 5698,
   CapabilityFPGAMemoryAttributesINTEL = 5824,
   CapabilityFPGALoopControlsINTEL = 5888,
+  CapabilityBlockingPipesINTEL = 5945,
   CapabilityMax = 0x7fffffff,
 };
 
@@ -1121,6 +1122,8 @@ enum Op {
   OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL = 5814,
   OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL = 5815,
   OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
+  OpReadPipeBlockingINTEL = 5946,
+  OpWritePipeBlockingINTEL = 5947,
   OpMax = 0x7fffffff,
 };
 

llvm-spirv/test/PipeBlocking.ll

@@ -0,0 +1,72 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc -spirv-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: llvm-spirv -r %t.spv -o %t.bc
+; RUN: llvm-dis < %t.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; ModuleID = 'test/CodeGenOpenCL/pipe_builtin.cl'
+source_filename = "test/CodeGenOpenCL/pipe_builtin.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+%opencl.pipe_ro_t = type opaque
+%opencl.pipe_wo_t = type opaque
+
+; CHECK-SPIRV: 2 Capability BlockingPipesINTEL
+; CHECK-SPIRV: 8 Extension "SPV_INTEL_blocking_pipes"
+; CHECK-SPIRV: 3 TypePipe {{[0-9]+}} 0
+; CHECK-SPIRV: 3 TypePipe {{[0-9]+}} 1
+; CHECK-SPIRV: 7 ReadPipeBlockingINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
+; CHECK-SPIRV: 7 WritePipeBlockingINTEL {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}} {{[0-9]+}}
+
+; CHECK-LLVM: %opencl.pipe_ro_t = type opaque
+; CHECK-LLVM: %opencl.pipe_wo_t = type opaque
+
+; CHECK-LLVM: %{{[0-9]+}} = call spir_func i32 @__read_pipe_bl_2(%opencl.pipe_ro_t addrspace(1)* %0, i8 addrspace(4)* %{{[0-9]+}}, i32 4, i32 4)
+; CHECK-LLVM: %{{[0-9]+}} = call spir_func i32 @__write_pipe_bl_2(%opencl.pipe_wo_t addrspace(1)* %0, i8 addrspace(4)* %{{[0-9]+}}, i32 4, i32 4)
+
+; Function Attrs: convergent noinline nounwind optnone
+define spir_func void @foo(%opencl.pipe_ro_t addrspace(1)* %p, i32 addrspace(1)* %ptr) #0 {
+entry:
+  %p.addr = alloca %opencl.pipe_ro_t addrspace(1)*, align 8
+  %ptr.addr = alloca i32 addrspace(1)*, align 8
+  store %opencl.pipe_ro_t addrspace(1)* %p, %opencl.pipe_ro_t addrspace(1)** %p.addr, align 8
+  store i32 addrspace(1)* %ptr, i32 addrspace(1)** %ptr.addr, align 8
+  %0 = load %opencl.pipe_ro_t addrspace(1)*, %opencl.pipe_ro_t addrspace(1)** %p.addr, align 8
+  %1 = load i32 addrspace(1)*, i32 addrspace(1)** %ptr.addr, align 8
+  %2 = addrspacecast i32 addrspace(1)* %1 to i8 addrspace(4)*
+  %3 = call spir_func i32 @_Z29__spirv_ReadPipeBlockingINTELIiEi8ocl_pipePT_ii(%opencl.pipe_ro_t addrspace(1)* %0, i8 addrspace(4)* %2, i32 4, i32 4)
+  ret void
+}
+
+declare dso_local spir_func i32 @_Z29__spirv_ReadPipeBlockingINTELIiEi8ocl_pipePT_ii(%opencl.pipe_ro_t addrspace(1)*, i8 addrspace(4)*, i32, i32)
+; CHECK-LLVM: declare spir_func i32 @__read_pipe_bl_2(%opencl.pipe_ro_t addrspace(1)*, i8 addrspace(4)*, i32, i32)
+
+; Function Attrs: convergent noinline nounwind optnone
+define spir_func void @boo(%opencl.pipe_wo_t addrspace(1)* %p, i32 addrspace(1)* %ptr) #0 {
+entry:
+  %p.addr = alloca %opencl.pipe_wo_t addrspace(1)*, align 8
+  %ptr.addr = alloca i32 addrspace(1)*, align 8
+  store %opencl.pipe_wo_t addrspace(1)* %p, %opencl.pipe_wo_t addrspace(1)** %p.addr, align 8
+  store i32 addrspace(1)* %ptr, i32 addrspace(1)** %ptr.addr, align 8
+  %0 = load %opencl.pipe_wo_t addrspace(1)*, %opencl.pipe_wo_t addrspace(1)** %p.addr, align 8
+  %1 = load i32 addrspace(1)*, i32 addrspace(1)** %ptr.addr, align 8
+  %2 = addrspacecast i32 addrspace(1)* %1 to i8 addrspace(4)*
+  %3 = call spir_func i32 @_Z30__spirv_WritePipeBlockingINTELIKiEi8ocl_pipePT_ii(%opencl.pipe_wo_t addrspace(1)* %0, i8 addrspace(4)* %2, i32 4, i32 4)
+  ret void
+}
+
+declare dso_local spir_func i32 @_Z30__spirv_WritePipeBlockingINTELIKiEi8ocl_pipePT_ii(%opencl.pipe_wo_t addrspace(1)*, i8 addrspace(4)*, i32, i32)
+; CHECK-LLVM: declare spir_func i32 @__write_pipe_bl_2(%opencl.pipe_wo_t addrspace(1)*, i8 addrspace(4)*, i32, i32)
+
+attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{!"clang version 9.0.0 (https://github.com/MrSidims/llvm.git c627b787284c5bcc917ea9742908baa1b856e176)"}

sycl/include/CL/__spirv/spirv_ops.hpp

@@ -190,6 +190,14 @@ template <typename dataT>
 extern int32_t __spirv_WritePipe(WPipeTy<dataT> Pipe, dataT *Data,
                                  int32_t Size, int32_t Alignment) noexcept;
 template <typename dataT>
+extern int32_t __spirv_ReadPipeBlockingINTEL(RPipeTy<dataT> Pipe, dataT *Data,
+                                             int32_t Size,
+                                             int32_t Alignment) noexcept;
+template <typename dataT>
+extern int32_t __spirv_WritePipeBlockingINTEL(WPipeTy<dataT> Pipe, dataT *Data,
+                                              int32_t Size,
+                                              int32_t Alignment) noexcept;
+template <typename dataT>
 extern RPipeTy<dataT> __spirv_CreatePipeFromPipeStorage_read(
     const ConstantPipeStorage *Storage) noexcept;
 template <typename dataT>

sycl/include/CL/sycl/pipes.hpp

@@ -54,8 +54,7 @@ template <class name, class dataT, int32_t min_capacity = 0> class pipe {
     RPipeTy<dataT> RPipe =
       __spirv_CreatePipeFromPipeStorage_read<dataT>(&m_Storage);
     dataT TempData;
-    // FIXME: this is workaround unless special SPIR-V decoration is implemented
-    while (!__spirv_ReadPipe(RPipe, &TempData, m_Size, m_Alignment));
+    __spirv_ReadPipeBlockingINTEL(RPipe, &TempData, m_Size, m_Alignment);
     return TempData;
 #else
     assert(!"Pipes are not supported on a host device!");
@@ -68,8 +67,7 @@ template <class name, class dataT, int32_t min_capacity = 0> class pipe {
 #ifdef __SYCL_DEVICE_ONLY__
     WPipeTy<dataT> WPipe =
       __spirv_CreatePipeFromPipeStorage_write<dataT>(&m_Storage);
-    // FIXME: this is workaround unless special SPIR-V decoration is implemented
-    while (!__spirv_WritePipe(WPipe, &Data, m_Size, m_Alignment));
+    __spirv_WritePipeBlockingINTEL(WPipe, &Data, m_Size, m_Alignment);
 #else
     assert(!"Pipes are not supported on a host device!");
 #endif // __SYCL_DEVICE_ONLY__