[SYCL][Driver] Disable "early" optimizations for Intel FPGA by default #2331
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…A target Enabling standard LLVM passes for SPIR target by default might have negative impact on the metadata added specifically for Intel FPGA target. We might switch it back to "ON" by default after more though validation.
mdtoguchi
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Aug 17, 2020
jsji
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Feb 1, 2024
Add support for checked matrix construct instruction. Specification draft: https://github.com/intel/llvm/blob/2fa153ee852ea3d7d64df097f1f494cddacee90e/sycl/doc/design/spirv-extensions/SPV_INTEL_joint_matrix.asciidoc Original commit: KhronosGroup/SPIRV-LLVM-Translator@a1b1f49
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Enabling standard LLVM passes for SPIR target by default might have
negative impact on the metadata added specifically for Intel FPGA
target. We might switch it back to "ON" by default after more though
validation.