[SYCL][FPGA] Add AST tests for loop attributes #11428
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Signed-off-by: Soumi Manna <soumi.manna@intel.com>
Signed-off-by: Soumi Manna <soumi.manna@intel.com>
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@intel/dpcpp-cfe-reviewers, please review. Thank you |
| [[intel::enable_loop_pipelining]] for (int n : c) { n *= 2; } | ||
| } | ||
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| void fpga_max_concurrency() { |
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Do we not have these (and following) tests already?
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Thanks @elizabethandrews for reviews. We did not have any AST tests for the FPGA Loop Attributes below:
[[intel::max_interleaving()]]
[[intel::loop_coalesce]]
[[intel::max_concurrency()]]
[[intel::initiation_interval()]],
[[intel::speculated_iterations()]].
Also some of other FPGA LOOP attributes that we did not have AST test which i plan to add later.
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ping @elizabethandrews. Thank you |
elizabethandrews
approved these changes
Oct 24, 2023
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This patch adds AST tests which we did not have before for the FPGA Loop Attributes below: