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[ESIMD] Use LLVM IR instead of GenX intrinsics for block loads/stores #10041
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This patch replaces usage of GenX intrinsics with regular LLVM IR. This change allowed to remove most of restrictions that previously accompanied slm_block_load/store() and block_load/store(). GPU RT/driver can lower 'load' instructions to one or several flat-loads or gather instructions depending on the target device, alignment and length. Same for 'store' instructions. Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
… missing Flags operand to block_load/store accepting local-accessor Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
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looks good, thanks!
Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
…p test Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
…not supported there Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
@turinevgeny , @fineg74 - please re-review this additional patch: 5c876ee |
Looks okay. |
… - USM and SLM (intel#10041) This patch replaces some uses of GenX intrinsics with regular LLVM IR. This change allowed to remove most of restrictions that previously accompanied slm_block_load/store() and block_load/store() accepting USM ptr. GPU RT/driver can lower 'load' instructions to one or several flat-loads and/or gather instructions depending on the target device, alignment and length. Same for 'store' instructions. --------- Signed-off-by: Vyacheslav N Klochkov <vyacheslav.n.klochkov@intel.com>
This patch replaces some uses of GenX intrinsics with regular LLVM IR.
This change allowed to remove most of restrictions that previously
accompanied slm_block_load/store() and block_load/store() accepting USM ptr.
GPU RT/driver can lower 'load' instructions to one or several flat-loads
and/or gather instructions depending on the target device, alignment and length.
Same for 'store' instructions.