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[SYCL] CPU JIT ICE in VPlan Vectorization Driver #823

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@agozillon

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@agozillon

I've attached an example SYCL program it's a pretty contrived and nonsensical example and will segfault if it actually runs properly. It's a problematic excerpt I found from a larger project that runs fine when using the Intel GPU OpenCL runtime but dies with the CPU implementation due to at minimum this segment I've found. Happy to redirect to the much larger project if that's of use.

However, for the moment at least on my machine and in my environment the attached example will result in what I think is a CPU JIT Compiler ICE:

   Stack dump:
      0.	Running pass 'Function Pass Manager' on module 'main'.
      1.	Running pass 'VPlan Vectorization Driver' on function ''
    Segmentation fault (core dumped)

I've unfortunately not had much time to dig into the IR after somewhat isolating the problem yet but the main problem area appears to be:

     for (; t < tfar; t += 1.0f) {
       f_tt = get(v);
       if (f_tt < 0)
         break;
     }
     t = t + 1.0f * f_tt / (1.0f - f_tt);

But there's a lot of very small things you can tweak in the example and it will compile properly, so it's been quite problematic to shrink it to a more concise code example sadly.

Currently using the most up-to-date Intel OpenCL CPU implementation and a recent (but not top of the tree, a few days or so old) version of the compiler.

VPlanFailure.zip

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OCL CPU Experimental RTIssues in Experimental Intel(R) CPU Runtime for OpenCL(TM) Applications with SYCL supportbugSomething isn't working

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