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[RISCV][GISel] Remove s32 support for G_ADD/SUB/AND/OR/XOR on RV64.
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This is consistent with other patches to remove s32 recently.
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@topperc
topperc committed Nov 12, 2024
1 parent eaed095 commit c280522
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Showing 39 changed files with 1,544 additions and 1,677 deletions.
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -132,10 +132,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0, nxv16p0};

getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
.legalFor({s32, sXLen})
.legalFor({sXLen})
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
.widenScalarToNextPow2(0)
.clampScalar(0, s32, sXLen);
.clampScalar(0, sXLen, sXLen);

getActionDefinitionsBuilder(
{G_UADDE, G_UADDO, G_USUBE, G_USUBO}).lower();
Expand Down
37 changes: 0 additions & 37 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Original file line number Diff line number Diff line change
Expand Up @@ -173,7 +173,6 @@ def : StPat<store, SD, GPR, PtrVT>;
// RV64 i32 patterns not used by SelectionDAG
//===----------------------------------------------------------------------===//

def simm12i32 : ImmLeaf<i32, [{return isInt<12>(Imm);}]>;
def uimm5i32 : ImmLeaf<i32, [{return isUInt<5>(Imm);}]>;

def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
Expand All @@ -196,35 +195,17 @@ def : Pat<(anyext GPR:$src), (COPY GPR:$src)>;
def : Pat<(sext GPR:$src), (ADDIW GPR:$src, 0)>;
def : Pat<(trunc GPR:$src), (COPY GPR:$src)>;

def : PatGprGpr<add, ADDW, i32, i32>;
def : PatGprGpr<sub, SUBW, i32, i32>;
def : PatGprGpr<and, AND, i32, i32>;
def : PatGprGpr<or, OR, i32, i32>;
def : PatGprGpr<xor, XOR, i32, i32>;
def : PatGprGpr<shl, SLLW, i32, i32>;
def : PatGprGpr<srl, SRLW, i32, i32>;
def : PatGprGpr<sra, SRAW, i32, i32>;

def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
def : Pat<(i32 (and GPR:$rs1, simm12i32:$imm)),
(ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
(ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;

def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)),
(SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)),
(SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)),
(SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>;

def : Pat<(i32 (and GPR:$rs, TrailingOnesMask:$mask)),
(SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
(i64 (XLenSubTrailingOnes $mask)))>;

// Use sext if the sign bit of the input is 0.
def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
}
Expand All @@ -245,31 +226,13 @@ def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
let Predicates = [HasStdExtZbb, IsRV64] in {
def : Pat<(i32 (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>;
def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;

def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
} // Predicates = [HasStdExtZbb, IsRV64]

let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in {
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (PACKW GPR:$rs, (XLenVT X0))>;
} // Predicates = [HasStdExtZbb, IsRV64]

let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]

let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(shl (i64 (zext GPR:$rs1)), uimm5:$shamt),
(SLLI_UW GPR:$rs1, uimm5:$shamt)>;

def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
(ADD_UW GPR:$rs1, GPR:$rs2)>;
def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;

foreach i = {1,2,3} in {
defvar shxadd = !cast<Instruction>("SH"#i#"ADD");
def : Pat<(i32 (add_like_non_imm12 (shl GPR:$rs1, (i32 i)), GPR:$rs2)),
(shxadd GPR:$rs1, GPR:$rs2)>;
}
}
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ define i8 @add_i8(i8 %a, i8 %b) {
;
; RV64IM-LABEL: add_i8:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = add i8 %a, %b
Expand All @@ -33,11 +33,11 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
;
; RV64IM-LABEL: add_i8_signext_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: slli a0, a0, 24
; RV64IM-NEXT: sraiw a0, a0, 24
; RV64IM-NEXT: slli a1, a1, 24
; RV64IM-NEXT: sraiw a1, a1, 24
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: slli a1, a1, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = sext i8 %a to i32
Expand All @@ -58,7 +58,7 @@ define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: andi a0, a0, 255
; RV64IM-NEXT: andi a1, a1, 255
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = zext i8 %a to i32
Expand All @@ -78,7 +78,7 @@ define i32 @add_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: add_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = add i32 %a, %b
Expand All @@ -93,7 +93,7 @@ define i32 @addi_i32(i32 %a) {
;
; RV64IM-LABEL: addi_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: addiw a0, a0, 1234
; RV64IM-NEXT: addi a0, a0, 1234
; RV64IM-NEXT: ret
entry:
%0 = add i32 %a, 1234
Expand All @@ -108,7 +108,7 @@ define i32 @sub_i32(i32 %a, i32 %b) {
;
; RV64IM-LABEL: sub_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: subw a0, a0, a1
; RV64IM-NEXT: sub a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = sub i32 %a, %b
Expand All @@ -123,7 +123,10 @@ define i32 @subi_i32(i32 %a) {
;
; RV64IM-LABEL: subi_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: addiw a0, a0, -1234
; RV64IM-NEXT: li a1, 1
; RV64IM-NEXT: slli a1, a1, 32
; RV64IM-NEXT: addi a1, a1, -1234
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
entry:
%0 = sub i32 %a, 1234
Expand All @@ -138,7 +141,7 @@ define i32 @neg_i32(i32 %a) {
;
; RV64IM-LABEL: neg_i32:
; RV64IM: # %bb.0: # %entry
; RV64IM-NEXT: negw a0, a0
; RV64IM-NEXT: neg a0, a0
; RV64IM-NEXT: ret
entry:
%0 = sub i32 0, %a
Expand Down
23 changes: 17 additions & 6 deletions llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV32
; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV64

; FIXME: andi a0, a0, 1 is unneeded
define i2 @bitreverse_i2(i2 %x) {
; RV32-LABEL: bitreverse_i2:
; RV32: # %bb.0:
Expand All @@ -18,12 +19,14 @@ define i2 @bitreverse_i2(i2 %x) {
; RV64-NEXT: andi a1, a1, 2
; RV64-NEXT: andi a0, a0, 3
; RV64-NEXT: srliw a0, a0, 1
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i2 @llvm.bitreverse.i2(i2 %x)
ret i2 %rev
}

; FIXME: andi a0, a0, 1 is unneeded
define i3 @bitreverse_i3(i3 %x) {
; RV32-LABEL: bitreverse_i3:
; RV32: # %bb.0:
Expand All @@ -44,12 +47,14 @@ define i3 @bitreverse_i3(i3 %x) {
; RV64-NEXT: andi a2, a0, 2
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: srliw a0, a0, 2
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i3 @llvm.bitreverse.i3(i3 %x)
ret i3 %rev
}

; FIXME: andi a0, a0, 1 is unneeded
define i4 @bitreverse_i4(i4 %x) {
; RV32-LABEL: bitreverse_i4:
; RV32: # %bb.0:
Expand Down Expand Up @@ -78,12 +83,14 @@ define i4 @bitreverse_i4(i4 %x) {
; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: srliw a0, a0, 3
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i4 @llvm.bitreverse.i4(i4 %x)
ret i4 %rev
}

; FIXME: andi a0, a0, 1 is unneeded
define i7 @bitreverse_i7(i7 %x) {
; RV32-LABEL: bitreverse_i7:
; RV32: # %bb.0:
Expand Down Expand Up @@ -128,6 +135,7 @@ define i7 @bitreverse_i7(i7 %x) {
; RV64-NEXT: or a2, a2, a3
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: srliw a0, a0, 6
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%rev = call i7 @llvm.bitreverse.i7(i7 %x)
Expand Down Expand Up @@ -177,24 +185,27 @@ define i24 @bitreverse_i24(i24 %x) {
; RV64-NEXT: and a0, a0, a2
; RV64-NEXT: srliw a0, a0, 16
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: lui a1, 1048335
; RV64-NEXT: addi a1, a1, 240
; RV64-NEXT: lui a1, 65521
; RV64-NEXT: addi a1, a1, -241
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: and a3, a1, a2
; RV64-NEXT: and a3, a0, a3
; RV64-NEXT: srliw a3, a3, 4
; RV64-NEXT: slli a0, a0, 4
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: lui a1, 1047757
; RV64-NEXT: addi a1, a1, -820
; RV64-NEXT: lui a1, 261939
; RV64-NEXT: addi a1, a1, 819
; RV64-NEXT: slli a1, a1, 2
; RV64-NEXT: and a3, a1, a2
; RV64-NEXT: and a3, a0, a3
; RV64-NEXT: srliw a3, a3, 2
; RV64-NEXT: slli a0, a0, 2
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: lui a1, 1047211
; RV64-NEXT: addiw a1, a1, -1366
; RV64-NEXT: lui a1, 523605
; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: slli a1, a1, 1
; RV64-NEXT: and a2, a1, a2
; RV64-NEXT: and a2, a0, a2
; RV64-NEXT: srliw a2, a2, 1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/GlobalISel/combine.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ define i32 @constant_to_rhs(i32 %x) {
; RV64-O0: # %bb.0:
; RV64-O0-NEXT: mv a1, a0
; RV64-O0-NEXT: li a0, 1
; RV64-O0-NEXT: addw a0, a0, a1
; RV64-O0-NEXT: add a0, a0, a1
; RV64-O0-NEXT: ret
;
; RV32-OPT-LABEL: constant_to_rhs:
Expand All @@ -30,7 +30,7 @@ define i32 @constant_to_rhs(i32 %x) {
;
; RV64-OPT-LABEL: constant_to_rhs:
; RV64-OPT: # %bb.0:
; RV64-OPT-NEXT: addiw a0, a0, 1
; RV64-OPT-NEXT: addi a0, a0, 1
; RV64-OPT-NEXT: ret
%a = add i32 1, %x
ret i32 %a
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/GlobalISel/constbarrier-rv64.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define i16 @constant_fold_barrier_i16(i16 %x, i16 %y) {
; RV64-NEXT: li a1, 1
; RV64-NEXT: slli a1, a1, 11
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: addiw a1, a1, 289
; RV64-NEXT: addi a1, a1, 289
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: ret
entry:
Expand Down
61 changes: 20 additions & 41 deletions llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -96,19 +96,12 @@ define ptr @freeze_ptr(ptr %x) {
%struct.T = type { i32, i32 }

define i32 @freeze_struct(ptr %p) {
; RV32-LABEL: freeze_struct:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_struct:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
; CHECK-LABEL: freeze_struct:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
%s = load %struct.T, ptr %p
%y1 = freeze %struct.T %s
%v1 = extractvalue %struct.T %y1, 0
Expand All @@ -118,19 +111,12 @@ define i32 @freeze_struct(ptr %p) {
}

define i32 @freeze_anonstruct(ptr %p) {
; RV32-LABEL: freeze_anonstruct:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_anonstruct:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
; CHECK-LABEL: freeze_anonstruct:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
%s = load {i32, i32}, ptr %p
%y1 = freeze {i32, i32} %s
%v1 = extractvalue {i32, i32} %y1, 0
Expand All @@ -155,9 +141,9 @@ define i32 @freeze_anonstruct2(ptr %p) {
; RV64-NEXT: lh a1, 4(a0)
; RV64-NEXT: lw a0, 0(a0)
; RV64-NEXT: lui a2, 16
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: addiw a2, a2, -1
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: addw a0, a0, a1
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: ret
%s = load {i32, i16}, ptr %p
%y1 = freeze {i32, i16} %s
Expand All @@ -169,19 +155,12 @@ define i32 @freeze_anonstruct2(ptr %p) {
}

define i32 @freeze_array(ptr %p) nounwind {
; RV32-LABEL: freeze_array:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: freeze_array:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a0, 4(a0)
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
; CHECK-LABEL: freeze_array:
; CHECK: # %bb.0:
; CHECK-NEXT: lw a1, 0(a0)
; CHECK-NEXT: lw a0, 4(a0)
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: ret
%s = load [2 x i32], ptr %p
%y1 = freeze [2 x i32] %s
%v1 = extractvalue [2 x i32] %y1, 0
Expand Down
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