Skip to content

Commit

Permalink
[ESIMD] Fix atomic_update with fcmpwr op, fix doxygen. (#6949)
Browse files Browse the repository at this point in the history
atomic_update with fcmpwr operation used incorrect order of "expected
value" and "new value" operands.

Also, documentation for 2-argument atomic_update was misleading -
specified incorrect parameter semantics for cmpxchg and fcmpwr
operation.

Signed-off-by: Konstantin S Bobrovsky <konstantin.s.bobrovsky@intel.com>
  • Loading branch information
kbobrovs authored Oct 4, 2022
1 parent f3cc5b1 commit 52923e6
Show file tree
Hide file tree
Showing 2 changed files with 9 additions and 6 deletions.
4 changes: 2 additions & 2 deletions sycl/include/sycl/ext/intel/esimd/memory.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -841,8 +841,8 @@ __ESIMD_API simd<Tx, N> atomic_update(Tx *p, simd<unsigned, N> offset,
/// @tparam N The number of memory locations to update.
/// @param p The USM pointer.
/// @param offset The vector of 32-bit offsets in bytes.
/// @param src0 The first additional argument (expected value).
/// @param src1 The second additional argument (new value).
/// @param src0 The first additional argument (new value).
/// @param src1 The second additional argument (expected value).
/// @param mask Operation mask, only locations with non-zero in the
/// corresponding mask element are updated.
/// @return A vector of the old values at the memory locations before the
Expand Down
11 changes: 7 additions & 4 deletions sycl/include/sycl/ext/intel/experimental/esimd/memory.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -1458,9 +1458,9 @@ lsc_atomic_update(T *p, __ESIMD_NS::simd<uint32_t, N> offsets,
/// @tparam L3H is L3 cache hint.
/// @param p is the base pointer.
/// @param offsets is the zero-based offsets.
/// @param src0 is the first atomic operand.
/// @param src1 is the second atomic operand.
/// @param pred is predicates.
/// @param src0 is the first atomic operand (expected value).
/// @param src1 is the second atomic operand (new value).
/// @param pred predicates.
///
template <__ESIMD_NS::atomic_op Op, typename T, int N,
lsc_data_size DS = lsc_data_size::default_size,
Expand Down Expand Up @@ -1695,8 +1695,11 @@ template <native::lsc::atomic_op Op, typename T, int N>
__ESIMD_API simd<T, N> atomic_update(T *p, simd<unsigned, N> offset,
simd<T, N> src0, simd<T, N> src1,
simd_mask<N> mask) {
// 2-argument lsc_atomic_update arguments order matches the standard one -
// expected value first, then new value. But atomic_update uses reverse order,
// hence the src1/src0 swap.
return __ESIMD_ENS::lsc_atomic_update<detail::to_atomic_op<Op>(), T, N>(
p, offset, src0, src1, mask);
p, offset, src1, src0, mask);
}

} // namespace esimd
Expand Down

0 comments on commit 52923e6

Please sign in to comment.