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[SYCL] Enable shuffle tests on HIP AMD. #487
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Corresponding work in llvm repo: intel/llvm#4664 |
Sorry if this is a silly question -- is this something you could work around by forwarding to an integer shuffle, or does compilation for these platforms fail as soon as they see a half type in a kernel? |
To expand a bit on that This is definitely an issue we need to figure out in the libclc build, but it's broader than just the subgroup builtins here, so I'm not sure if it's worth doing a workaround just for this, I also ran into it in intel/llvm#4223 a while back. |
Got it. Thanks for the explanation. FWIW, this sort of thing also impacts the CUDA backend. The ability to generate floating-point atomics, for example (see intel/llvm#3276) depends on the SM architecture that libclc is being built for. A general solution for multi-versioning and/or controlling the architecture used by libclc would be useful to multiple backends. |
Thanks @npmiller for the clarification, I'll update the comments to reflect that. |
Even though `gfx908` and `gfx906` support halfs, libspirv is currently built with `tahiti` as the target CPU, which means that clang rejects AMD built-ins using halfs, for that reason half support has to stay disabled.
Even though `gfx908` and `gfx906` support halfs, libspirv is currently built with `tahiti` as the target CPU, which means that clang rejects AMD built-ins using halfs, for that reason half support has to stay disabled.
Even though
gfx908
andgfx906
support halfs, libspirv is currentlybuilt with
tahiti
as the target CPU, which means that clang rejectsAMD built-ins using halfs, for that reason half support has to stay
disabled.