Add soft reset

src/common/lpspi.rs

@@ -450,7 +450,7 @@ impl<P, const N: u8> Lpspi<P, N> {
 
         // Reset and disable
         ral::modify_reg!(ral::lpspi, spi.lpspi, CR, MEN: MEN_0, RST: RST_1);
-        while ral::read_reg!(ral::lpspi, spi.lpspi, CR, MEN == MEN_1) {}
+        while spi.is_enabled() {}
         ral::modify_reg!(ral::lpspi, spi.lpspi, CR, RST: RST_0, RTF: RTF_1, RRF: RRF_1);
 
         // Configure master mode
@@ -479,6 +479,11 @@ impl<P, const N: u8> Lpspi<P, N> {
     }
 
     /// Enable (`true`) or disable (`false`) the peripheral.
+    ///
+    /// Note that disabling does not take effect immediately; instead the
+    /// peripheral finishes the current transfer and then disables itself.
+    /// It is required to check [`is_enabled`] repeatedly until the
+    /// peripheral is actually disabled.
     pub fn set_enable(&mut self, enable: bool) {
         ral::modify_reg!(ral::lpspi, self.lpspi, CR, MEN: enable as u32)
     }
@@ -494,6 +499,46 @@ impl<P, const N: u8> Lpspi<P, N> {
         }
     }
 
+    /// Cancel the current transfer and force the driver back into idle
+    /// state.
+    ///
+    /// This should be done whenever an error occurred.
+    pub fn soft_reset(&mut self) {
+        // Backup previous registers
+        let ier = ral::read_reg!(ral::lpspi, self.lpspi, IER);
+        let der = ral::read_reg!(ral::lpspi, self.lpspi, DER);
+        let cfgr0 = ral::read_reg!(ral::lpspi, self.lpspi, CFGR0);
+        let cfgr1 = ral::read_reg!(ral::lpspi, self.lpspi, CFGR1);
+        let dmr0 = ral::read_reg!(ral::lpspi, self.lpspi, DMR0);
+        let dmr1 = ral::read_reg!(ral::lpspi, self.lpspi, DMR1);
+        let ccr = ral::read_reg!(ral::lpspi, self.lpspi, CCR);
+        let fcr = ral::read_reg!(ral::lpspi, self.lpspi, FCR);
+
+        // Backup enabled state
+        let enabled = self.is_enabled();
+
+        // Reset and disable
+        ral::modify_reg!(ral::lpspi, self.lpspi, CR, MEN: MEN_0, RST: RST_1);
+        while self.is_enabled() {}
+        ral::modify_reg!(ral::lpspi, self.lpspi, CR, RST: RST_0, RTF: RTF_1, RRF: RRF_1);
+
+        // Reset fifos
+        ral::modify_reg!(ral::lpspi, self.lpspi, CR, RTF: RTF_1, RRF: RRF_1);
+
+        // Restore settings
+        ral::write_reg!(ral::lpspi, self.lpspi, IER, ier);
+        ral::write_reg!(ral::lpspi, self.lpspi, DER, der);
+        ral::write_reg!(ral::lpspi, self.lpspi, CFGR0, cfgr0);
+        ral::write_reg!(ral::lpspi, self.lpspi, CFGR1, cfgr1);
+        ral::write_reg!(ral::lpspi, self.lpspi, DMR0, dmr0);
+        ral::write_reg!(ral::lpspi, self.lpspi, DMR1, dmr1);
+        ral::write_reg!(ral::lpspi, self.lpspi, CCR, ccr);
+        ral::write_reg!(ral::lpspi, self.lpspi, FCR, fcr);
+
+        // Restore enabled state
+        self.set_enable(enabled);
+    }
+
     /// Release the SPI driver components.
     ///
     /// This does not change any component state; it releases the components as-is.