GitHub - hvwyl/armv4-core: 32 bit CPU with ARM instructions implementation in Verilog

hvwyl / armv4-core Public

32 bit CPU with ARM instructions implementation in Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 29 Commits
armbuild		armbuild
alu.v		alu.v
alu_tb.v		alu_tb.v
armv4core.v		armv4core.v
armv4core_instructions.html		armv4core_instructions.html
armv4core_tb.v		armv4core_tb.v
cpsr.v		cpsr.v
def.v		def.v
ex_stage.v		ex_stage.v
ex_wb.v		ex_wb.v
forward_ctrl.v		forward_ctrl.v
hazard_ctrl.v		hazard_ctrl.v
id_ex.v		id_ex.v
id_stage.v		id_stage.v
if_id.v		if_id.v
irq_ctrl.v		irq_ctrl.v
ldm_ctrl.v		ldm_ctrl.v
ldm_ctrl_tb.v		ldm_ctrl_tb.v
memctrl.v		memctrl.v
one_detector.v		one_detector.v
one_detector_tb.v		one_detector_tb.v
pc.v		pc.v
registers.v		registers.v
shift.v		shift.v
shift_tb.v		shift_tb.v
shift_unit.v		shift_unit.v
swp_ctrl.v		swp_ctrl.v
wb_stage.v		wb_stage.v