Digital System Design Lab

Overview

This repository contains the projects and experiments conducted in the Digital System Design Lab at the University of Computer Engineering. The lab focuses on various aspects of digital system design using Quartus® II software. A total of 10 experiments are included, each designed to enhance understanding of digital design principles and practical applications.

Experiments

Each experiment consists of two main components:

1. Report File: A detailed report documenting the experiment, including objectives, methodology, results, and conclusions.
2. Verilog Files: The Verilog code used to implement the designs for the experiment.

List of Experiments

Each experiment is organized in its own folder, named according to the experiment number and title. Inside each folder, you will find the report and the Verilog files.

1. Experiment 1: Basic Logic Gates

   • Folder: 01_BasicLogicGates/
     • Report: 01_BasicLogicGates_Report.pdf
     • Verilog File: 01_BasicLogicGates.v

2. Experiment 2: Combinational Circuits

   • Folder: 02_CombinationalCircuits/
     • Report: 02_CombinationalCircuits_Report.pdf
     • Verilog File: 02_CombinationalCircuits.v

3. Experiment 3: Sequential Circuits

   • Folder: 03_SequentialCircuits/
     • Report: 03_SequentialCircuits_Report.pdf
     • Verilog File: 03_SequentialCircuits.v

4. Experiment 4: Finite State Machines

   • Folder: 04_FiniteStateMachines/
     • Report: 04_FiniteStateMachines_Report.pdf
     • Verilog File: 04_FiniteStateMachines.v

5. Experiment 5: ALU Design

   • Folder: 05_ALU_Design/
     • Report: 05_ALU_Design_Report.pdf
     • Verilog File: 05_ALU_Design.v

6. Experiment 6: Memory Design

   • Folder: 06_MemoryDesign/
     • Report: 06_MemoryDesign_Report.pdf
     • Verilog File: 06_MemoryDesign.v

7. Experiment 7: FPGA Implementation

   • Folder: 07_FPGImplementation/
     • Report: 07_FPGImplementation_Report.pdf
     • Verilog File: 07_FPGImplementation.v

8. Experiment 8: UART Communication

   • Folder: 08_UARTCommunication/
     • Report: 08_UARTCommunication_Report.pdf
     • Verilog File: 08_UARTCommunication.v

9. Experiment 9: Digital Filters

   • Folder: 09_DigitalFilters/
     • Report: 09_DigitalFilters_Report.pdf
     • Verilog File: 09_DigitalFilters.v

10. Experiment 10: System on Chip (SoC)

    • Folder: 10_SystemOnChip/
      • Report: 10_SystemOnChip_Report.pdf
      • Verilog File: 10_SystemOnChip.v

Source Files

In addition to the experiments, there is a folder named SourceFiles that contains previously existing source codes that were utilized in the experiments. This folder serves as a reference for the foundational code and designs that support the current experiments.

Folder Structure

/Digital-System-Design-Lab
│
├── /SourceFiles
│   ├── [ExistingSource1].v
│   ├── [ExistingSource2].v
│   └── ...
│
├── /01_BasicLogicGates
│   ├── 01_BasicLogicGates_Report.pdf
│   └── 01_BasicLogicGates.v
│
├── /02_CombinationalCircuits
│   ├── 02_CombinationalCircuits_Report.pdf
│   └── 02_CombinationalCircuits.v
│
└── ...

File Naming Convention

To maintain organization and clarity, please follow the naming convention outlined below for all files related to the experiments:

[ExperimentNumber]_[ExperimentTitle]_[Type].pdf or .v

Example:

• For Experiment 1 titled "Basic Logic Gates":
  • Report: 01_BasicLogicGates_Report.pdf
  • Verilog File: 01_BasicLogicGates.v

Notes:

• Replace [ExperimentNumber] with the corresponding experiment number (01, 02, ..., 10).
• Replace [ExperimentTitle] with a short, descriptive title of the experiment.
• Use _Report for report files and .v for Verilog files.

Installation

To set up the project locally, clone the repository and follow the instructions in the installation guide.

Usage

Detailed instructions on how to run the experiments and examples of usage can be found in the usage documentation.

Contributing

Contributions are welcome! Please read the contributing guidelines for more information.

License

This project is licensed under the MIT License. See the LICENSE file for details.

For more information, please refer to the GitHub repository.