Synthesis and P&R: Move closer to OpenROAD-flow-scripts

Synthesis:
This commit adds a custom abc.script from OpenROAD-flow-scripts.
This commit also modifies the synthesis script. It adds 2 new steps:
extract adders - it tries to map addition chains to PDK specific
full adder and half adder improving overall performance.
Runs only when `adder_mapping` attr is provided.
tie logic cells - it runs `hilomap` pass.

P&R:
This commit changes output_db file extention to .odb.
OpenROAD file explorer only allows for .odb to be opened from GUI.

Allow user to disable `improve_placement` pass during
resize step. It can cause cell overlapping both by
not maintaining sufficient cell to cell spacing as well as
true cell overlapping.
Some other minor changes to the P&R scripts.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>

place_and_route/build_defs.bzl

@@ -105,5 +105,6 @@ place_and_route = rule(
         "sink_clustering_size": attr.int(doc = "Clock tree synthesis sink group size"),
         "sink_clustering_max_diameter": attr.int(doc = "Clock tree synthesis sink group desired diamater in microns"),
         "min_pin_distance": attr.string(doc = "The minimum distance in microns between pins around the outside of the block."),
+        "enable_improve_placement": attr.bool(default=True, doc = "Enable/Disable improve_placement pass.")
     },
 )

place_and_route/open_road.bzl

@@ -210,9 +210,9 @@ def openroad_command(ctx, commands, input_db = None, step_name = None, inputs =
 
     output_db = None
     if step_name:
-        output_db = ctx.actions.declare_file("{}__{}.db".format(ctx.attr.name, step_name))
+        output_db = ctx.actions.declare_file("{}__{}.odb".format(ctx.attr.name, step_name))
     else:
-        output_db = ctx.actions.declare_file("{}{}.db".format(input_hash, command_hash))
+        output_db = ctx.actions.declare_file("{}{}.odb".format(input_hash, command_hash))
 
     real_commands = []
     if input_db:

place_and_route/private/clock_tree_synthesis.bzl

@@ -47,6 +47,7 @@ def clock_tree_synthesis(ctx, open_road_info):
             sink_clustering_max_diameter = "-sink_clustering_max_diameter {}".format(ctx.attr.sink_clustering_max_diameter) if ctx.attr.sink_clustering_max_diameter else "",
         ),
         "set_propagated_clock [all_clocks]",
+        "estimate_parasitics -placement",
         "repair_clock_nets",
         "estimate_parasitics -placement",
     ] + placement_padding_struct.commands + [

place_and_route/private/detailed_routing.bzl

@@ -55,8 +55,10 @@ def detailed_routing(ctx, open_road_info):
         if detailed_routing_configs.enable_via_gen:
             detailed_routing_args += " -disable_via_gen "
 
-    open_road_commands = timing_setup_command_struct.commands
-    open_road_commands.append("detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args))
+    open_road_commands = timing_setup_command_struct.commands + [
+        "set_propagated_clock [all_clocks]",
+        "detailed_route -output_drc {} {}".format(output_drc.path, detailed_routing_args)
+    ]
     density_fill_config = None
     if open_road_configuration.density_fill_config:
         density_fill_config = open_road_configuration.density_fill_config.files.to_list()[0]

place_and_route/private/global_placement.bzl

@@ -40,7 +40,7 @@ def global_placement(ctx, open_road_info):
             pad_left = open_road_configuration.global_placement_cell_pad,
             pad_right = open_road_configuration.global_placement_cell_pad,
         ),
-        "remove_buffers",
+        "estimate_parasitics -placement",
     ]
 
     command_output = openroad_command(

place_and_route/private/resize.bzl

@@ -51,7 +51,7 @@ def resize(ctx, open_road_info):
         ),
     ] + placement_padding_struct.commands + [
         "detailed_placement",
-        "improve_placement",
+        "improve_placement" if ctx.attr.enable_improve_placement else "",
         "optimize_mirroring",
         "check_placement -verbose",
         "report_checks -path_delay min_max -format full_clock_expanded -fields {input_pin slew capacitance} -digits 3",

synthesis/BUILD

@@ -22,6 +22,7 @@ package(
 )
 
 exports_files(["synth.tcl"])
+exports_files(["abc.script"])
 
 pkg_tar(
     name = "yosys",

synthesis/abc.script

@@ -0,0 +1,45 @@
+&get -n
+&st
+&dch
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+&get -n
+&st
+&syn2
+&if -g -K 6
+&synch2
+&nf
+&put
+buffer -c
+topo
+stime -c
+upsize -c
+dnsize -c

synthesis/build_defs.bzl

@@ -90,14 +90,18 @@ def _synthesize_design_impl(ctx):
     default_liberty_file = ctx.attr.standard_cells[StandardCellInfo].default_corner.liberty
 
     synth_tcl = ctx.file.synth_tcl
+    abc_script = ctx.file.abc_script
 
     inputs = []
     inputs.extend(verilog_files)
     inputs.append(verilog_flist)
     inputs.append(uhdm_flist)
     inputs.extend(uhdm_files)
     inputs.append(synth_tcl)
+    inputs.append(abc_script)
     inputs.append(default_liberty_file)
+    if ctx.attr.adder_mapping:
+        inputs.append(ctx.file.adder_mapping)
 
     (tool_inputs, input_manifests) = ctx.resolve_tools(tools = [ctx.attr.yosys_tool])
 
@@ -125,11 +129,21 @@ def _synthesize_design_impl(ctx):
         "OUTPUT": output_file,
         "LIBERTY": default_liberty_file,
         "DONT_USE_ARGS": dont_use_args,
+        "ABC_SCRIPT": abc_script,
     }
 
     if ctx.attr.target_clock_period_pico_seconds:
         script_env_files["CLOCK_PERIOD"] = str(ctx.attr.target_clock_period_pico_seconds)
 
+    if or_config.tie_low_port:
+        script_env_files["TIELO_CELL_AND_PORT"] = str(or_config.tie_low_port)
+
+    if or_config.tie_high_port:
+        script_env_files["TIEHI_CELL_AND_PORT"] = str(or_config.tie_high_port)
+
+    if ctx.attr.adder_mapping:
+        script_env_files["ADDER_MAPPING"] = str(ctx.file.adder_mapping.path)
+
     env = {
         "YOSYS_DATDIR": yosys_runfiles_dir + "/at_clifford_yosys/techlibs/",
         "ABC": yosys_runfiles_dir + "/edu_berkeley_abc/abc",
@@ -253,6 +267,15 @@ synthesize_rtl = rule(
             allow_single_file = True,
             doc = "Tcl synthesis script compatible with the environment-variable API of synth.tcl",
         ),
+        "abc_script": attr.label(
+            default = Label("//synthesis:abc.script"),
+            allow_single_file = True,
+            doc = "ABC script",
+        ),
+        "adder_mapping": attr.label(
+            allow_single_file = True,
+            doc = "Verilog file that maps yosys adder to PDK adders."
+        ),
         "target_clock_period_pico_seconds": attr.int(doc = "target clock period in picoseconds"),
         "output_file_name": attr.string(doc = "The output file name."),
     },

synthesis/synth.tcl

@@ -72,16 +72,47 @@ yosys synth -top $top
 yosys opt_clean -purge
 yosys autoname
 
+# Technology mapping of adders
+if {[info exists ::env(ADDER_MAPPING)] && [file isfile $::env(ADDER_MAPPING)]} {
+  # extract the full adders
+  extract_fa
+  # map full adders
+  techmap -map $::env(ADDER_MAPPING)
+  techmap
+  # Quick optimization
+  opt -fast -purge
+}
+
 # mapping to liberty
 set liberty $::env(LIBERTY)
 dfflibmap -liberty $liberty
 
+opt
+
 if { [info exists ::env(CLOCK_PERIOD) ] } {
   abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS)
 } else {
   abc -liberty $liberty -dff -g aig {*}$::env(DONT_USE_ARGS)
 }
 
+setundef -zero
+
+splitnets
+
+opt_clean -purge
+
+if {[info exists ::env(TIEHI_CELL_AND_PORT)] && [info exists ::env(TIELO_CELL_AND_PORT)]} {
+  hilomap \
+        -hicell {*}[split $::env(TIEHI_CELL_AND_PORT) "/"] \
+        -locell {*}[split $::env(TIELO_CELL_AND_PORT) "/"]
+} elseif { [info exists ::env(TIEHI_CELL_AND_PORT)] } {
+  hilomap \
+        -hicell {*}$::env(TIEHI_CELL_AND_PORT)
+} elseif { [info exists ::env(TIELO_CELL_AND_PORT)] } {
+  hilomap \
+        -locell {*}$::env(TIELO_CELL_AND_PORT)
+}
+
 # Remove internal only aliases for public nets and then give created instances
 # useful names. At this stage it is anything generated by the techmapping
 # passes.
@@ -101,7 +132,7 @@ if { [info exists ::env(STATS_JSON) ] } {
 read_liberty -lib -ignore_miss_func $liberty
 ltp -noff $top
 
-yosys log -n Flop count:\ 
+yosys log -n Flop count:\
 yosys select -count t:*__df* t:DFF* t:*_DFF* t:*_SDFF* t:*_ADFF* t:*dff
 
 set base_liberty [file tail $liberty]