pic32 sanity fixes #1451
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pic32 sanity fixes #1451
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_mips is provided by xc32-gcc
TU_ASSERTS added to detect transfer inconsistency.
When transfer was finished rx_fifo_read() read all that was to read RXPKTRDY was cleared allowing next packet to be received. Then xfer_complete was called. Interrupt for OUT endpoint was left enable, that would not be a problem if data was handled fast and new transfer was scheduled. For MSC when host sends a lot of data this interrupt that was enabled could cause epn_handle_rx_int() to be called after transfer was completed and next was not scheduled yet. Without TU_ASSERT that was added to detect this, incoming data was written past buffer provided by user code resulting in random memory corruption. This just blocks RX interrupt when transfer is finished, and also only unmasked rx interrupts are handled.
hathach
approved these changes
May 24, 2022
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Describe the PR
For PIC32 OUT packets that were sent from host and not handled
fast enough could lead to memory corruption.
When transfer was complete OUT endpoint was left open for
host to send more data (which is fine and allow for faster transfer).
however if data packet arrived before new transfer was scheduled
code was reading endpoint and writing past buffer that was filled
with previous transfer data.
To prevent such scenario RX interrupt is disabled when transfer is
finished (data can still arrived at endpoint).
Interrupt handler now handles only enabled RX transfers.
When new transfer starts it will enable interrupt (as it was doing
so far).
Two first commits are just to improve error detection.
Third fixes overwrite problem.
Additional context
This was detected when MSC device was used.