Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
	common/cmd_fpga.c
	drivers/usb/host/ohci-at91.c

.gitignore

@@ -80,5 +80,11 @@ cscope.*
 /ctags
 /etags
 
+# gnu global files
+GPATH
+GRTAGS
+GSYMS
+GTAGS
+
 # spl ais files
 /spl/*.ais

MAINTAINERS

@@ -1086,9 +1086,19 @@ Unknown / orphaned boards:
 #	Board		CPU						#
 #########################################################################
 
-Graeme Russ <graeme.russ@gmail.com>
+Simon Glass <sjg@chromium.org>
 
-	eNET		AMD SC520
+	chromebook-x86	Coreboot runs first, then U-Boot
+			Supports Intel Sandy Bridge / Ivy Bridge so far
+
+			Chromebooks for x86, including:
+				Samsung Series 5 Chromebook
+				Acer AC700 Chromebook
+				Acer C7 Chromebook
+				Samsung Chromebook 550
+				HP Pavillion Chromebook
+				Acer C710 Chromebook
+				Chromebook Pixel
 
 #########################################################################
 # MIPS Systems:								#
@@ -1353,6 +1363,17 @@ Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 
 	openrisc-generic	OpenRISC
 
+#########################################################################
+# Sandbox:								#
+#									#
+# Maintainer Name, Email Address					#
+#	Board		CPU						#
+#########################################################################
+
+Simon Glass <sjg@chromium.org>
+
+	sandbox		sandbox
+
 #########################################################################
 # End of MAINTAINERS list						#
 #########################################################################

MAKEALL

@@ -267,12 +267,6 @@ LIST_8xx="$(boards_by_cpu mpc8xx)"
 
 LIST_4xx="$(boards_by_cpu ppc4xx)"
 
-#########################################################################
-## MPC8220 Systems
-#########################################################################
-
-LIST_8220="$(boards_by_cpu mpc8220)"
-
 #########################################################################
 ## MPC824x Systems
 #########################################################################
@@ -324,7 +318,6 @@ LIST_powerpc="		\
 	${LIST_512x}	\
 	${LIST_5xxx}	\
 	${LIST_8xx}	\
-	${LIST_8220}	\
 	${LIST_824x}	\
 	${LIST_8260}	\
 	${LIST_83xx}	\

README

@@ -201,7 +201,6 @@ Directory Hierarchy:
       /mpc5xx		Files specific to Freescale MPC5xx CPUs
       /mpc5xxx		Files specific to Freescale MPC5xxx CPUs
       /mpc8xx		Files specific to Freescale MPC8xx CPUs
-      /mpc8220		Files specific to Freescale MPC8220 CPUs
       /mpc824x		Files specific to Freescale MPC824x CPUs
       /mpc8260		Files specific to Freescale MPC8260 CPUs
       /mpc85xx		Files specific to Freescale MPC85xx CPUs
@@ -899,6 +898,7 @@ The following options need to be configured:
 		CONFIG_CMD_SF		* Read/write/erase SPI NOR flash
 		CONFIG_CMD_SHA1SUM	  print sha1 memory digest
 					  (requires CONFIG_CMD_MEMORY)
+		CONFIG_CMD_SOFTSWITCH	* Soft switch setting command for BF60x
 		CONFIG_CMD_SOURCE	  "source" command Support
 		CONFIG_CMD_SPI		* SPI serial bus support
 		CONFIG_CMD_TFTPSRV	* TFTP transfer in server mode
@@ -2997,6 +2997,12 @@ FIT uImage format:
 		use an arch-specific makefile fragment instead, for
 		example if more than one image needs to be produced.
 
+		CONFIG_FIT_SPL_PRINT
+		Printing information about a FIT image adds quite a bit of
+		code to SPL. So this is normally disabled in SPL. Use this
+		option to re-enable it. This will affect the output of the
+		bootm command when booting a FIT image.
+
 Modem Support:
 --------------
 
@@ -5062,7 +5068,7 @@ On some platforms, it's possible to boot Linux zImage. This is done
 using the "bootz" command. The syntax of "bootz" command is the same
 as the syntax of "bootm" command.
 
-Note, defining the CONFIG_SUPPORT_INITRD_RAW allows user to supply
+Note, defining the CONFIG_SUPPORT_RAW_INITRD allows user to supply
 kernel with raw initrd images. The syntax is slightly different, the
 address of the initrd must be augmented by it's size, in the following
 format: "<initrd addres>:<initrd size>".

api/api_platform-powerpc.c

@@ -55,8 +55,6 @@ int platform_sys_info(struct sys_info *si)
 #define bi_bar	bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
-#elif defined(CONFIG_MPC8220)
-#define bi_bar	bi_mbar_base
 #endif
 
 #if defined(bi_bar)

arch/arm/include/asm/bootm.h

@@ -1,4 +1,7 @@
-/* Copyright (C) 2011
+/*
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
  * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -19,8 +22,55 @@
 #ifndef ARM_BOOTM_H
 #define ARM_BOOTM_H
 
-#ifdef CONFIG_USB_DEVICE
 extern void udc_disconnect(void);
+
+#if defined(CONFIG_SETUP_MEMORY_TAGS) || \
+		defined(CONFIG_CMDLINE_TAG) || \
+		defined(CONFIG_INITRD_TAG) || \
+		defined(CONFIG_SERIAL_TAG) || \
+		defined(CONFIG_REVISION_TAG)
+# define BOOTM_ENABLE_TAGS		1
+#else
+# define BOOTM_ENABLE_TAGS		0
+#endif
+
+#ifdef CONFIG_SETUP_MEMORY_TAGS
+# define BOOTM_ENABLE_MEMORY_TAGS	1
+#else
+# define BOOTM_ENABLE_MEMORY_TAGS	0
+#endif
+
+#ifdef CONFIG_CMDLINE_TAG
+ #define BOOTM_ENABLE_CMDLINE_TAG	1
+#else
+ #define BOOTM_ENABLE_CMDLINE_TAG	0
+#endif
+
+#ifdef CONFIG_INITRD_TAG
+ #define BOOTM_ENABLE_INITRD_TAG	1
+#else
+ #define BOOTM_ENABLE_INITRD_TAG	0
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+ #define BOOTM_ENABLE_SERIAL_TAG	1
+void get_board_serial(struct tag_serialnr *serialnr);
+#else
+ #define BOOTM_ENABLE_SERIAL_TAG	0
+static inline void get_board_serial(struct tag_serialnr *serialnr)
+{
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+ #define BOOTM_ENABLE_REVISION_TAG	1
+u32 get_board_rev(void);
+#else
+ #define BOOTM_ENABLE_REVISION_TAG	0
+static inline u32 get_board_rev(void)
+{
+	return 0;
+}
 #endif
 
 #endif

arch/arm/include/asm/u-boot-arm.h

@@ -54,8 +54,6 @@ int	arch_early_init_r(void);
 int	board_init(void);
 int	dram_init (void);
 void	dram_init_banksize (void);
-void	setup_serial_tag (struct tag **params);
-void	setup_revision_tag (struct tag **params);
 
 /* cpu/.../interrupt.c */
 int	arch_interrupt_init	(void);

arch/arm/lib/Makefile

@@ -45,6 +45,7 @@ endif
 COBJS-y += bss.o
 
 COBJS-y	+= bootm.o
+COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
 COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o

board/sorcery/sorcery.c → arch/arm/lib/bootm-fdt.c

@@ -1,6 +1,16 @@
 /*
- * (C) Copyright 2004, Freescale Inc.
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com
+ * Copyright (c) 2013, Google Inc.
+ *
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *  - Added prep subcommand support
+ *  - Reorganized source - modeled after powerpc version
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * Copyright (C) 2001  Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -22,47 +32,21 @@
  */
 
 #include <common.h>
-#include <mpc8220.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <pci.h>
-#include <netdev.h>
-
-phys_size_t initdram (int board_type)
-{
-	ulong size;
-
-	size = dramSetup ();
+#include <fdt_support.h>
 
-	return get_ram_size(CONFIG_SYS_SDRAM_BASE, size);
-}
+DECLARE_GLOBAL_DATA_PTR;
 
-int checkboard (void)
+int arch_fixup_memory_node(void *blob)
 {
-	puts ("Board: Sorcery-C MPC8220\n");
-
-	return 0;
-}
-
-#if defined(CONFIG_PCI)
-/*
- * Initialize PCI devices, report devices found.
- */
-static struct pci_controller hose;
+	bd_t *bd = gd->bd;
+	int bank;
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
 
-#endif /* CONFIG_PCI */
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] = bd->bi_dram[bank].start;
+		size[bank] = bd->bi_dram[bank].size;
+	}
 
-void pci_init_board (void)
-{
-#ifdef CONFIG_PCI
-	extern void pci_mpc8220_init (struct pci_controller *hose);
-	pci_mpc8220_init (&hose);
-#endif /* CONFIG_PCI */
-}
-
-int board_eth_init(bd_t *bis)
-{
-	/* Initialize built-in FEC first */
-	cpu_eth_init(bis);
-	return pci_eth_init(bis);
+	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
 }