Merge branch 'master' of git://git.denx.de/u-boot-arm

Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>

.gitignore

@@ -44,7 +44,6 @@
 /u-boot.dtb
 /u-boot.sb
 /u-boot.geany
-/include/u-boot.lst
 
 #
 # Generated files

MAINTAINERS

@@ -606,6 +606,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
 
 	igep0020	ARM ARMV7 (OMAP3xx SoC)
 	igep0030	ARM ARMV7 (OMAP3xx SoC)
+	igep0032	ARM ARMV7 (OMAP3xx SoC)
 
 Eric Benard <eric@eukrea.com>
 
@@ -974,6 +975,8 @@ Tom Warren <twarren@nvidia.com>
 
 	harmony		Tegra20 (ARM7 & A9 Dual Core)
 	seaboard	Tegra20 (ARM7 & A9 Dual Core)
+	cardhu		Tegra30 (ARM7 & A9 Quad Core)
+	dalmore		Tegra114 (ARM7 & A15 Quad Core)
 
 Tom Warren <twarren@nvidia.com>
 Stephen Warren <swarren@nvidia.com>
@@ -1035,6 +1038,14 @@ Pali Rohár <pali.rohar@gmail.com>
 
 	nokia_rx51	ARM ARMV7 (OMAP34xx SoC)
 
+Eric Nelson <eric.nelson@boundarydevices.com>
+	nitrogen6dl		i.MX6DL		1GB
+	nitrogen6dl2g		i.MX6DL		2GB
+	nitrogen6q		i.MX6Q/6D	1GB
+	nitrogen6q2g    	i.MX6Q/6D	2GB
+	nitrogen6s		i.MX6S		512MB
+	nitrogen6s1g		i.MX6S		1GB
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

Makefile

@@ -464,8 +464,8 @@ $(obj)u-boot.img:	$(obj)u-boot.bin
 			sed -e 's/"[	 ]*$$/ for $(BOARD) board"/') \
 		-d $< $@
 
-$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
-		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
+$(obj)u-boot.imx: $(obj)u-boot.bin depend
+		$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
 
 $(obj)u-boot.kwb:       $(obj)u-boot.bin
 		$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
@@ -556,10 +556,8 @@ GEN_UBOOT = \
 			$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
 else
 GEN_UBOOT = \
-		UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
-		sed  -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
-			$$UNDEF_LST $(__OBJS) \
+			$(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
 endif
@@ -592,11 +590,7 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
 $(LDSCRIPT):	depend
 		$(MAKE) -C $(dir $@) $(notdir $@)
 
-# The following line expands into whole rule which generates u-boot.lst,
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
-$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+$(obj)u-boot.lds: $(LDSCRIPT)
 		$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
 
 nand_spl:	$(TIMESTAMP_FILE) $(VERSION_FILE) depend
@@ -832,7 +826,6 @@ clean:
 	       $(obj)board/matrix_vision/*/bootscript.img		  \
 	       $(obj)board/voiceblue/eeprom 				  \
 	       $(obj)u-boot.lds						  \
-	       $(obj)include/u-boot.lst			  		  \
 	       $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]	  \
 	       $(obj)arch/blackfin/cpu/init.{lds,elf}
 	@rm -f $(obj)include/bmp_logo.h
@@ -870,7 +863,7 @@ clobber:	tidy
 	@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
 	@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
 	@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
-	@rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
+	@rm -f $(obj)spl/u-boot-spl.lds
 	@rm -f $(obj)MLO MLO.byteswap
 	@rm -f $(obj)SPL
 	@rm -f $(obj)tools/xway-swap-bytes

README

@@ -485,6 +485,16 @@ The following options need to be configured:
 		Thumb2 this flag will result in Thumb2 code generated by
 		GCC.
 
+		CONFIG_ARM_ERRATA_742230
+		CONFIG_ARM_ERRATA_743622
+		CONFIG_ARM_ERRATA_751472
+
+		If set, the workarounds for these ARM errata are applied early
+		during U-Boot startup. Note that these options force the
+		workarounds to be applied; no CPU-type/version detection
+		exists, unlike the similar options in the Linux kernel. Do not
+		set these options unless they apply!
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ
 
@@ -1533,6 +1543,17 @@ CBFS (Coreboot Filesystem) support
 		allows for a "silent" boot where a splash screen is
 		loaded very quickly after power-on.
 
+		CONFIG_SPLASHIMAGE_GUARD
+
+		If this option is set, then U-Boot will prevent the environment
+		variable "splashimage" from being set to a problematic address
+		(see README.displaying-bmps and README.arm-unaligned-accesses).
+		This option is useful for targets where, due to alignment
+		restrictions, an improperly aligned BMP image will cause a data
+		abort. If you think you will not have problems with unaligned
+		accesses (for example because your toolchain prevents them)
+		there is no need to set this option.
+
 		CONFIG_SPLASH_SCREEN_ALIGN
 
 		If this option is set the splash image can be freely positioned
@@ -1553,6 +1574,14 @@ CBFS (Coreboot Filesystem) support
 			=> vertically centered image
 			   at x = dspWidth - bmpWidth - 9
 
+		CONFIG_SPLASH_SCREEN_PREPARE
+
+		If this option is set then the board_splash_screen_prepare()
+		function, which must be defined in your code, is called as part
+		of the splash screen display sequence. It gives the board an
+		opportunity to prepare the splash image data before it is
+		processed and sent to the frame buffer by U-Boot.
+
 - Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
 
 		If this option is set, additionally to standard BMP

arch/arm/cpu/arm1136/mx35/generic.c

@@ -519,7 +519,7 @@ u32 spl_boot_device(void)
 		case RCSR_MEM_TYPE_NOR:
 			return BOOT_DEVICE_NOR;
 		case RCSR_MEM_TYPE_ONENAND:
-			return BOOT_DEVICE_ONE_NAND;
+			return BOOT_DEVICE_ONENAND;
 		default:
 			return BOOT_DEVICE_NONE;
 		}

arch/arm/cpu/arm720t/tegra114/cpu.c

@@ -201,6 +201,7 @@ void t114_init_clocks(void)
 	reset_set_enable(PERIPH_ID_MSELECT, 0);
 	reset_set_enable(PERIPH_ID_EMC1, 0);
 	reset_set_enable(PERIPH_ID_MC1, 0);
+	reset_set_enable(PERIPH_ID_DVFS, 0);
 
 	debug("t114_init_clocks exit\n");
 }
@@ -269,6 +270,8 @@ void powerup_cpus(void)
 
 void start_cpu(u32 reset_vector)
 {
+	u32 imme, inst;
+
 	debug("start_cpu entry, reset_vector = %x\n", reset_vector);
 
 	t114_init_clocks();
@@ -285,12 +288,38 @@ void start_cpu(u32 reset_vector)
 	/* Take CPU(s) out of reset */
 	remove_cpu_resets();
 
+	/* Set the entry point for CPU execution from reset */
+
 	/*
-	 * Set the entry point for CPU execution from reset,
-	 *  if it's a non-zero value.
+	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
+	 * See nvbug 1193357 for details.
 	 */
-	if (reset_vector)
-		writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+	/* mov r0, #lsb(reset_vector) */
+	imme = reset_vector & 0xffff;
+	inst = imme & 0xfff;
+	inst |= ((imme >> 12) << 16);
+	inst |= 0xe3000000;
+	writel(inst, 0x4003fff0);
+
+	/* movt r0, #msb(reset_vector) */
+	imme = (reset_vector >> 16) & 0xffff;
+	inst = imme & 0xfff;
+	inst |= ((imme >> 12) << 16);
+	inst |= 0xe3400000;
+	writel(inst, 0x4003fff4);
+
+	/* bx r0 */
+	writel(0xe12fff10, 0x4003fff8);
+
+	/* b -12 */
+	imme = (u32)-20;
+	inst = (imme >> 2) & 0xffffff;
+	inst |= 0xea000000;
+	writel(inst, 0x4003fffc);
+
+	/* Write to orignal location for compatibility */
+	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
 
 	/* If the CPU(s) don't already have power, power 'em up */
 	powerup_cpus();

arch/arm/cpu/arm920t/ep93xx/u-boot.lds

@@ -51,7 +51,7 @@ SECTIONS
 
 	. = ALIGN(4);
 	.u_boot_list : {
-	#include <u-boot.lst>
+		KEEP(*(SORT(.u_boot_list*)));
 	}
 
 	. = ALIGN(4);

arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c

@@ -61,20 +61,20 @@ char *get_cpu_name()
 	if (cpu_is_at91sam9x5()) {
 		switch (extension_id) {
 		case ARCH_EXID_AT91SAM9G15:
-			return CONFIG_SYS_AT91_G15_CPU_NAME;
+			return "AT91SAM9G15";
 		case ARCH_EXID_AT91SAM9G25:
-			return CONFIG_SYS_AT91_G25_CPU_NAME;
+			return "AT91SAM9G25";
 		case ARCH_EXID_AT91SAM9G35:
-			return CONFIG_SYS_AT91_G35_CPU_NAME;
+			return "AT91SAM9G35";
 		case ARCH_EXID_AT91SAM9X25:
-			return CONFIG_SYS_AT91_X25_CPU_NAME;
+			return "AT91SAM9X25";
 		case ARCH_EXID_AT91SAM9X35:
-			return CONFIG_SYS_AT91_X35_CPU_NAME;
+			return "AT91SAM9X35";
 		default:
-			return CONFIG_SYS_AT91_UNKNOWN_CPU;
+			return "Unknown CPU type";
 		}
 	} else {
-		return CONFIG_SYS_AT91_UNKNOWN_CPU;
+		return "Unknown CPU type";
 	}
 }
 
@@ -246,14 +246,14 @@ void at91_macb_hw_init(void)
 #ifndef CONFIG_RMII
 	/* Only emac0 support MII */
 	if (has_emac0()) {
-		at91_set_b_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
-		at91_set_b_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
-		at91_set_b_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
-		at91_set_b_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
-		at91_set_b_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
-		at91_set_b_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
-		at91_set_b_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
-		at91_set_b_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
+		at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* ECRS */
+		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* ECOL */
+		at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* ERX2 */
+		at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* ERX3 */
+		at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* ERXCK */
+		at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* ETX2 */
+		at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* ETX3 */
+		at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* ETXER */
 	}
 #endif
 }

arch/arm/cpu/arm926ejs/config.mk

@@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
 
 ifneq ($(CONFIG_IMX_CONFIG),)
 
-ALL-y	+= $(OBJTREE)/u-boot.imx
+ALL-y	+= $(obj)u-boot.imx
 
 endif

arch/arm/cpu/arm926ejs/mxs/clock.c

@@ -289,7 +289,8 @@ static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
 void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
 	struct mxs_ssp_regs *ssp_regs;
-	const uint32_t sspclk = mxs_get_sspclk(bus);
+	const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus);
+	const uint32_t sspclk = mxs_get_sspclk(clk);
 	uint32_t reg;
 	uint32_t divide, rate, tgtclk;
 

arch/arm/cpu/arm926ejs/mxs/mxs_init.h

@@ -30,7 +30,7 @@ void early_delay(int delay);
 
 void mxs_power_init(void);
 
-#ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
+#ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
 void mxs_power_wait_pswitch(void);
 #else
 static inline void mxs_power_wait_pswitch(void) { }

arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c

@@ -27,6 +27,7 @@
 #include <config.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
 #include <linux/compiler.h>
 
 #include "mxs_init.h"
@@ -119,6 +120,10 @@ static void initialize_dram_values(void)
 		writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 
 #ifdef CONFIG_MX23
+	/*
+	 * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last
+	 * element to be set
+	 */
 	writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
 #endif
 }
@@ -229,21 +234,28 @@ static void mx23_mem_setup_vddmem(void)
 	struct mxs_power_regs *power_regs =
 		(struct mxs_power_regs *)MXS_POWER_BASE;
 
-	writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+	writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
 		POWER_VDDMEMCTRL_ENABLE_ILIMIT |
 		POWER_VDDMEMCTRL_ENABLE_LINREG |
 		POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
 		&power_regs->hw_power_vddmemctrl);
 
 	early_delay(10000);
 
-	writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
+	writel((0x10 << POWER_VDDMEMCTRL_TRG_OFFSET) |
 		POWER_VDDMEMCTRL_ENABLE_LINREG,
 		&power_regs->hw_power_vddmemctrl);
 }
 
 static void mx23_mem_init(void)
 {
+	/*
+	 * Reset/ungate the EMI block. This is essential, otherwise the system
+	 * suffers from memory instability. This thing is mx23 specific and is
+	 * no longer present on mx28.
+	 */
+	mxs_reset_block((struct mxs_register_32 *)MXS_EMI_BASE);
+
 	mx23_mem_setup_vddmem();
 
 	/*

arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

@@ -921,7 +921,7 @@ void mxs_power_init(void)
 	early_delay(1000);
 }
 
-#ifdef	CONFIG_SPL_MX28_PSWITCH_WAIT
+#ifdef	CONFIG_SPL_MXS_PSWITCH_WAIT
 void mxs_power_wait_pswitch(void)
 {
 	struct mxs_power_regs *power_regs =