Cleaned up stale references to unused/deprecated functionality for ca…

…cheing page tables

README.txt

@@ -152,7 +152,6 @@ Options:
                         A URN location from which to load an address space
   -w, --write           Enable write support
   --dtb=DTB             DTB Address
-  --cache-dtb           Cache virtual to physical mappings
   --output=text         Output in this format (format support is module
                         specific)
   --output-file=OUTPUT_FILE

volatility/plugins/addrspaces/amd64.py

@@ -60,7 +60,6 @@ class AMD64PagedMemory(paged.AbstractWritablePagedMemory):
        "Windows Internals, 5th Edition", Microsoft Press, 2009.
     """
     order = 60
-    cache = False
     pae = False
     checkname = 'AMD64ValidAS'
     paging_address_space = True

volatility/plugins/addrspaces/arm.py

@@ -28,25 +28,12 @@
 
 class ArmAddressSpace(paged.AbstractWritablePagedMemory):
     order = 800
-    cache = False
     pae = False
     paging_address_space = True
     checkname = 'ArmValidAS'
     minimum_size = 0x1000
     alignment_gcd = 0x1000
 
-    def _cache_values(self):
-        '''
-        buf = self.base.read(self.dtb, 0x1000)
-        if buf is None:
-            self.cache = False
-        else:
-            self.pde_cache = struct.unpack('<' + 'I' * 0x400, buf)
-    
-        '''
-        #print "skipping cache"
-        pass
-
     def read_long_phys(self, addr):
         '''
         Returns an unsigned 32-bit integer from the address addr in

volatility/plugins/addrspaces/intel.py

@@ -69,7 +69,6 @@ class IA32PagedMemory(paged.AbstractWritablePagedMemory):
        "Windows Internals, 5th Edition", Microsoft Press, 2009.
     """
     order = 70
-    cache = False
     pae = False
     paging_address_space = True
     checkname = 'IA32ValidAS'

volatility/plugins/addrspaces/macho.py

@@ -143,7 +143,6 @@ class MachOAddressSpace(addrspace.AbstractRunBasedMemory):
     From there we can translate between incoming address requests to memory contents
     """
     order = 1
-    cache = False
     pae = True
     checkname = 'MachOValidAS'
 

volatility/plugins/addrspaces/paged.py

@@ -27,7 +27,6 @@ class AbstractPagedMemory(addrspace.AbstractVirtualAddressSpace):
         
     Note: Pages can be of any size
     """
-    cache = False
     checkname = "Intel"
 
     def __init__(self, base, config, dtb = 0, skip_as_check = False, *args, **kwargs):
@@ -44,12 +43,6 @@ def __init__(self, base, config, dtb = 0, skip_as_check = False, *args, **kwargs
 
         self.as_assert(self.dtb != None, "No valid DTB found")
 
-        # The caching code must be in a separate function to allow the
-        # PAE code, which inherits us, to have its own code.
-        self.cache = config.CACHE_DTB
-        if self.cache:
-            self._cache_values()
-
         if not skip_as_check:
             volmag = obj.VolMagic(self)
             if hasattr(volmag, self.checkname):
@@ -61,12 +54,6 @@ def __init__(self, base, config, dtb = 0, skip_as_check = False, *args, **kwargs
         #self.pagefile = config.PAGEFILE
         self.name = 'Kernel AS'
 
-    def _cache_values(self):
-        '''
-        We cache the top level tables to avoid having to 
-        look them up later.
-        '''
-
     def load_dtb(self):
         """Loads the DTB as quickly as possible from the config, then the base, then searching for it"""
         try:
@@ -97,9 +84,6 @@ def register_options(config):
         config.add_option("DTB", type = 'int', default = 0,
                           help = "DTB Address")
 
-        config.add_option("CACHE-DTB", action = "store_false", default = True,
-                          help = "Cache virtual to physical mappings")
-
     def vtop(self, addr):
         """Abstract function that converts virtual (paged) addresses to physical addresses"""
         pass