ASR 64-bit lane not available in sse instruction (ocaml-flambda#3413)

gretay-js · Jan 10, 2025 · b8fd6dc · b8fd6dc
1 parent 17dc9b6
commit b8fd6dc
Showing 1 changed file with 7 additions and 6 deletions.
diff --git a/backend/amd64/simd_selection.ml b/backend/amd64/simd_selection.ml
@@ -589,13 +589,14 @@ let vectorize_operation (width_type : Vectorize_utils.Width_in_bits.t)
       let sse_op =
         match width_type with
         | W128 -> assert false
-        | W64 -> assert false
-        | W32 -> SRA_i32
-        | W16 -> SRA_i16
-        | W8 -> assert false
+        | W64 -> None
+        | W32 -> Some SRA_i32
+        | W16 -> Some SRA_i16
+        | W8 -> None
       in
-      Operation.Specific (Isimd (SSE2 sse_op))
-      |> make_default ~arg_count ~res_count
+      Option.bind sse_op (fun sse_op ->
+          Operation.Specific (Isimd (SSE2 sse_op))
+          |> make_default ~arg_count ~res_count)
     | Icomp (Isigned intcomp) -> (
       match intcomp with
       | Ceq ->