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Automated rollback of commit f9489e2d0c0ba4e0adee3158a6f7c356ef4af785. #3834

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4 changes: 2 additions & 2 deletions docs_src/codegen_options.md
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Expand Up @@ -171,8 +171,8 @@ control the scheduler.

- `--codegen_version` is the version of codegen pipeline to use; options are 0
(default), 1 (original codegen path), 1.5 (refactored codegen), or 2
(revised codegen with a new architecture). Currently default means v1
(original).
(revised codegen with a new architecture). Currently default means v1.5
(refactored).

- `--merge_on_mutual_exclusion` runs a mutual-exclusion analysis and attempts
to merge any I/O operations on the same channel that can be proven to be
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6 changes: 3 additions & 3 deletions xls/build_rules/tests/BUILD
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Expand Up @@ -150,22 +150,22 @@ xls_dslx_verilog(
check_sha256sum_test(
name = "add_one_pipeline_rtl_v_sha256sum_test",
src = ":add_one_pipeline_rtl.sv",
sha256sum = "7230178ff270fa174805ff808bbe927c19a13961fc4e957e59aa434569e36caf",
sha256sum = "9be677d6561ae03dc21b759629e17336b30c6f21159e9b8bb56495917a51abee",
)

# Build a frozen file generated with a build rule.
check_sha256sum_frozen(
name = "add_one_pipeline_rtl_v_sha256sum_frozen",
src = ":add_one_pipeline_rtl.sv",
frozen_file = ":add_one_pipeline_rtl.frozen.v",
sha256sum = "7230178ff270fa174805ff808bbe927c19a13961fc4e957e59aa434569e36caf",
sha256sum = "9be677d6561ae03dc21b759629e17336b30c6f21159e9b8bb56495917a51abee",
)

# Test with a frozen checksum file generated with a check_sha256sum_frozen rule.
check_sha256sum_test(
name = "add_one_pipeline_rtl_frozen_v_sha256sum_test",
src = ":add_one_pipeline_rtl.frozen.v",
sha256sum = "7230178ff270fa174805ff808bbe927c19a13961fc4e957e59aa434569e36caf",
sha256sum = "9be677d6561ae03dc21b759629e17336b30c6f21159e9b8bb56495917a51abee",
)

sh_test(
Expand Down
32 changes: 16 additions & 16 deletions xls/codegen/testdata/assertions_comb_multiple_ifdef_guards.svtxt
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Expand Up @@ -2,24 +2,24 @@ module assertions_top(
input wire [31:0] y,
output wire [31:0] out
);
wire [30:0] add_195;
wire ult_202;
wire [30:0] add_209;
wire ult_206;
wire nand_211;
wire nand_212;
assign add_195 = y[31:1] + 31'h7fff_fffb;
assign ult_202 = y < 32'h0000_0014;
assign add_209 = y[31:1] + 31'h0000_000f;
assign ult_206 = y < 32'h0000_000a;
assign nand_211 = ~(y > 32'h0000_0009 & ult_202 & {add_195, y[0]} > 32'h0000_0004);
assign nand_212 = ~(ult_206 & y > 32'h0000_0004);
assign out = ult_206 ? {add_209, y[0]} : y & {32{ult_202}};
wire [30:0] add_202;
wire ult_204;
wire [30:0] add_211;
wire ult_214;
wire nand_221;
wire nand_222;
assign add_202 = y[31:1] + 31'h7fff_fffb;
assign ult_204 = y < 32'h0000_0014;
assign add_211 = y[31:1] + 31'h0000_000f;
assign ult_214 = y < 32'h0000_000a;
assign nand_221 = ~(y > 32'h0000_0009 & ult_204 & {add_202, y[0]} > 32'h0000_0004);
assign nand_222 = ~(ult_214 & y > 32'h0000_0004);
assign out = ult_214 ? {add_211, y[0]} : y & {32{ult_204}};
`ifdef ASSERT_ON
`ifndef SYNTHESIS
y_ge_than_21: assert final ($isunknown(ult_202) || ult_202) else $fatal(0, "Assertion failure via fail! @ xls/examples/assertions/assertions.x:32:14-32:37");
__assertions__main_0___itok__assertions__main___itok__assertions__main_0___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_211) || nand_211) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
__assertions__main_0___itok__assertions__main___itok__assertions__main_1___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_212) || nand_212) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
y_ge_than_21: assert final ($isunknown(ult_204) || ult_204) else $fatal(0, "Assertion failure via fail! @ xls/examples/assertions/assertions.x:32:14-32:37");
__assertions__main_0___itok__assertions__main___itok__assertions__main_0___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_221) || nand_221) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
__assertions__main_0___itok__assertions__main___itok__assertions__main_1___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_222) || nand_222) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
`endif // SYNTHESIS
`endif // ASSERT_ON
endmodule
32 changes: 16 additions & 16 deletions xls/codegen/testdata/assertions_comb_no_ifdef_guards.svtxt
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Expand Up @@ -2,20 +2,20 @@ module assertions_top(
input wire [31:0] y,
output wire [31:0] out
);
wire [30:0] add_195;
wire ult_202;
wire [30:0] add_209;
wire ult_206;
wire nand_211;
wire nand_212;
assign add_195 = y[31:1] + 31'h7fff_fffb;
assign ult_202 = y < 32'h0000_0014;
assign add_209 = y[31:1] + 31'h0000_000f;
assign ult_206 = y < 32'h0000_000a;
assign nand_211 = ~(y > 32'h0000_0009 & ult_202 & {add_195, y[0]} > 32'h0000_0004);
assign nand_212 = ~(ult_206 & y > 32'h0000_0004);
assign out = ult_206 ? {add_209, y[0]} : y & {32{ult_202}};
y_ge_than_21: assert final ($isunknown(ult_202) || ult_202) else $fatal(0, "Assertion failure via fail! @ xls/examples/assertions/assertions.x:32:14-32:37");
__assertions__main_0___itok__assertions__main___itok__assertions__main_0___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_211) || nand_211) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
__assertions__main_0___itok__assertions__main___itok__assertions__main_1___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_212) || nand_212) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
wire [30:0] add_202;
wire ult_204;
wire [30:0] add_211;
wire ult_214;
wire nand_221;
wire nand_222;
assign add_202 = y[31:1] + 31'h7fff_fffb;
assign ult_204 = y < 32'h0000_0014;
assign add_211 = y[31:1] + 31'h0000_000f;
assign ult_214 = y < 32'h0000_000a;
assign nand_221 = ~(y > 32'h0000_0009 & ult_204 & {add_202, y[0]} > 32'h0000_0004);
assign nand_222 = ~(ult_214 & y > 32'h0000_0004);
assign out = ult_214 ? {add_211, y[0]} : y & {32{ult_204}};
y_ge_than_21: assert final ($isunknown(ult_204) || ult_204) else $fatal(0, "Assertion failure via fail! @ xls/examples/assertions/assertions.x:32:14-32:37");
__assertions__main_0___itok__assertions__main___itok__assertions__main_0___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_221) || nand_221) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
__assertions__main_0___itok__assertions__main___itok__assertions__main_1___itok__assertions__func_0__32_x_less_than_5: assert final ($isunknown(nand_222) || nand_222) else $fatal(0, "Assertion failure via assert! @ xls/examples/assertions/assertions.x:21:12-21:40");
endmodule
130 changes: 67 additions & 63 deletions xls/codegen/testdata/verilog_conversion_test_MultiProcDirectConnect.svtxt
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Expand Up @@ -10,47 +10,49 @@ module pipelined_proc__1(
output wire [31:0] internal,
output wire internal_vld
);
reg [31:0] p0_tuple_index_25;
reg p0_valid;
reg [31:0] p0_tuple_index_4;
reg [31:0] __in_reg;
reg __in_valid_reg;
reg [31:0] __internal_reg;
reg __internal_valid_reg;
reg p1_inputs_valid;
wire internal_valid_inv;
wire internal_valid_load_en;
wire internal_load_en;
wire p1_stage_done;
wire p1_not_valid;
wire p0_enable;
wire p0_data_enable;
wire not_167;
wire stage_outputs_valid_1;
wire stage_outputs_ready_0;
wire p0_stage_done__1;
wire in_valid_inv;
wire in_valid_load_en;
wire in_load_en;
wire or_188;
assign internal_valid_inv = ~__internal_valid_reg;
assign internal_valid_load_en = internal_rdy | internal_valid_inv;
assign internal_load_en = p0_valid & internal_valid_load_en;
assign p1_stage_done = p0_valid & internal_load_en;
assign p1_not_valid = ~p0_valid;
assign p0_enable = p1_stage_done | p1_not_valid;
assign p0_data_enable = p0_enable & __in_valid_reg;
assign internal_load_en = p1_inputs_valid & internal_valid_load_en;
assign not_167 = ~p1_inputs_valid;
assign stage_outputs_valid_1 = p1_inputs_valid & internal_load_en;
assign stage_outputs_ready_0 = not_167 | stage_outputs_valid_1;
assign p0_stage_done__1 = __in_valid_reg & stage_outputs_ready_0;
assign in_valid_inv = ~__in_valid_reg;
assign in_valid_load_en = p0_data_enable | in_valid_inv;
assign in_valid_load_en = p0_stage_done__1 | in_valid_inv;
assign in_load_en = in_vld & in_valid_load_en;
assign or_188 = p0_stage_done__1 | stage_outputs_valid_1;
always_ff @ (posedge clk) begin
if (rst) begin
p0_tuple_index_25 <= 32'h0000_0000;
p0_valid <= 1'h0;
p0_tuple_index_4 <= 32'h0000_0000;
__in_reg <= 32'h0000_0000;
__in_valid_reg <= 1'h0;
__internal_reg <= 32'h0000_0000;
__internal_valid_reg <= 1'h0;
p1_inputs_valid <= 1'h0;
end else begin
p0_tuple_index_25 <= p0_data_enable ? __in_reg : p0_tuple_index_25;
p0_valid <= p0_enable ? __in_valid_reg : p0_valid;
p0_tuple_index_4 <= p0_stage_done__1 ? __in_reg : p0_tuple_index_4;
__in_reg <= in_load_en ? in : __in_reg;
__in_valid_reg <= in_valid_load_en ? in_vld : __in_valid_reg;
__internal_reg <= internal_load_en ? p0_tuple_index_25 : __internal_reg;
__internal_valid_reg <= internal_valid_load_en ? p0_valid : __internal_valid_reg;
__internal_reg <= internal_load_en ? p0_tuple_index_4 : __internal_reg;
__internal_valid_reg <= internal_valid_load_en ? p1_inputs_valid : __internal_valid_reg;
p1_inputs_valid <= or_188 ? p0_stage_done__1 : p1_inputs_valid;
end
end
assign in_rdy = in_load_en;
Expand All @@ -69,47 +71,49 @@ module proc_out(
output wire [31:0] out,
output wire out_vld
);
reg [31:0] p0_tuple_index_85;
reg p0_valid;
reg [31:0] p0_tuple_index_9;
reg [31:0] __internal_reg;
reg __internal_valid_reg;
reg [31:0] __out_reg;
reg __out_valid_reg;
reg p1_inputs_valid;
wire out_valid_inv;
wire out_valid_load_en;
wire out_load_en;
wire p1_stage_done;
wire p1_not_valid;
wire p0_enable;
wire p0_data_enable;
wire not_222;
wire stage_outputs_valid_1;
wire stage_outputs_ready_0;
wire p0_stage_done__1;
wire internal_valid_inv;
wire internal_valid_load_en;
wire internal_load_en;
wire or_243;
assign out_valid_inv = ~__out_valid_reg;
assign out_valid_load_en = out_rdy | out_valid_inv;
assign out_load_en = p0_valid & out_valid_load_en;
assign p1_stage_done = p0_valid & out_load_en;
assign p1_not_valid = ~p0_valid;
assign p0_enable = p1_stage_done | p1_not_valid;
assign p0_data_enable = p0_enable & __internal_valid_reg;
assign out_load_en = p1_inputs_valid & out_valid_load_en;
assign not_222 = ~p1_inputs_valid;
assign stage_outputs_valid_1 = p1_inputs_valid & out_load_en;
assign stage_outputs_ready_0 = not_222 | stage_outputs_valid_1;
assign p0_stage_done__1 = __internal_valid_reg & stage_outputs_ready_0;
assign internal_valid_inv = ~__internal_valid_reg;
assign internal_valid_load_en = p0_data_enable | internal_valid_inv;
assign internal_valid_load_en = p0_stage_done__1 | internal_valid_inv;
assign internal_load_en = internal_vld & internal_valid_load_en;
assign or_243 = p0_stage_done__1 | stage_outputs_valid_1;
always_ff @ (posedge clk) begin
if (rst) begin
p0_tuple_index_85 <= 32'h0000_0000;
p0_valid <= 1'h0;
p0_tuple_index_9 <= 32'h0000_0000;
__internal_reg <= 32'h0000_0000;
__internal_valid_reg <= 1'h0;
__out_reg <= 32'h0000_0000;
__out_valid_reg <= 1'h0;
p1_inputs_valid <= 1'h0;
end else begin
p0_tuple_index_85 <= p0_data_enable ? __internal_reg : p0_tuple_index_85;
p0_valid <= p0_enable ? __internal_valid_reg : p0_valid;
p0_tuple_index_9 <= p0_stage_done__1 ? __internal_reg : p0_tuple_index_9;
__internal_reg <= internal_load_en ? internal : __internal_reg;
__internal_valid_reg <= internal_valid_load_en ? internal_vld : __internal_valid_reg;
__out_reg <= out_load_en ? p0_tuple_index_85 : __out_reg;
__out_valid_reg <= out_valid_load_en ? p0_valid : __out_valid_reg;
__out_reg <= out_load_en ? p0_tuple_index_9 : __out_reg;
__out_valid_reg <= out_valid_load_en ? p1_inputs_valid : __out_valid_reg;
p1_inputs_valid <= or_243 ? p0_stage_done__1 : p1_inputs_valid;
end
end
assign internal_rdy = internal_load_en;
Expand All @@ -128,35 +132,35 @@ module pipelined_proc(
output wire [31:0] out,
output wire out_vld
);
wire instantiation_output_136;
wire [31:0] instantiation_output_141;
wire instantiation_output_142;
wire instantiation_output_149;
wire [31:0] instantiation_output_153;
wire instantiation_output_154;
wire instantiation_output_143;
wire [31:0] instantiation_output_147;
wire instantiation_output_148;
wire instantiation_output_128;
wire [31:0] instantiation_output_133;
wire instantiation_output_134;
wire instantiation_output_141;
wire [31:0] instantiation_output_145;
wire instantiation_output_146;
wire instantiation_output_135;
wire [31:0] instantiation_output_139;
wire instantiation_output_140;

// ===== Instantiations
pipelined_proc__1 pipelined_proc__1_inst0 (
.rst(rst),
.in(in),
.in_vld(in_vld),
.internal_rdy(instantiation_output_143),
.in_rdy(instantiation_output_136),
.internal(instantiation_output_141),
.internal_vld(instantiation_output_142),
.internal_rdy(instantiation_output_135),
.in_rdy(instantiation_output_128),
.internal(instantiation_output_133),
.internal_vld(instantiation_output_134),
.clk(clk)
);
proc_out proc_out_inst1 (
.rst(rst),
.internal(instantiation_output_147),
.internal_vld(instantiation_output_148),
.internal(instantiation_output_139),
.internal_vld(instantiation_output_140),
.out_rdy(out_rdy),
.internal_rdy(instantiation_output_149),
.out(instantiation_output_153),
.out_vld(instantiation_output_154),
.internal_rdy(instantiation_output_141),
.out(instantiation_output_145),
.out_vld(instantiation_output_146),
.clk(clk)
);
xls_fifo_wrapper #(
Expand All @@ -168,14 +172,14 @@ module pipelined_proc(
) fifo_internal (
.clk(clk),
.rst(rst),
.push_data(instantiation_output_141),
.push_valid(instantiation_output_142),
.pop_ready(instantiation_output_149),
.push_ready(instantiation_output_143),
.pop_data(instantiation_output_147),
.pop_valid(instantiation_output_148)
.push_data(instantiation_output_133),
.push_valid(instantiation_output_134),
.pop_ready(instantiation_output_141),
.push_ready(instantiation_output_135),
.pop_data(instantiation_output_139),
.pop_valid(instantiation_output_140)
);
assign in_rdy = instantiation_output_136;
assign out = instantiation_output_153;
assign out_vld = instantiation_output_154;
assign in_rdy = instantiation_output_128;
assign out = instantiation_output_145;
assign out_vld = instantiation_output_146;
endmodule
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