Avoid name and keyword collisions in generated verilog. #2229
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cdleary
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May 21, 2025
xls/codegen/block_stitching_pass.cc
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| @@ -501,8 +501,10 @@ absl::StatusOr<bool> BlockStitchingPass::RunInternal( | |||
| return absl::UnimplementedError( | |||
| "Splitting outputs is not supported by block stitching."); | |||
| } | |||
| // std::string top_block_name(options.codegen_options.module_name().value_or( | |||
| // SanitizeVerilogIdentifier(context.top_block()->name()))); | |||
cdleary
reviewed
May 21, 2025
| @@ -357,6 +359,10 @@ std::string SanitizeIdentifier(std::string_view name) { | |||
| sanitized[i] = '_'; | |||
| } | |||
| } | |||
| if ((system_verilog ? SystemVerilogKeywords() : VerilogKeywords()) | |||
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Maybe just add a comment to note that our policy is to put an underscore suffix on any keyword collisions? (Similar to the explainer comment above)
cdleary
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May 21, 2025
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Add a name uniquer on ModuleBuilder to prevent accidental collisions of identifiers in verilog modules (regs, wires, etc). Other fixes, cleanups: * xls::verilog::SanitizeIdentifier renamed to SanitizeVerilogIdentifier to distinguish it from other uses of sanitize. * SanitizeVerilogIdentifier now sanitizes keywords. * Raise an error if port names collide rather than silently renaming because port names are part of the interface and should not be changed. * Don't call SanitizeVerilogIdentifer during block creation. We have a separate pass which handes that (NameLeagalizationPass). Fixes #2209. Fixes #805 PiperOrigin-RevId: 762532280
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Avoid name and keyword collisions in generated verilog.
Add a name uniquer on ModuleBuilder to prevent accidental collisions of identifiers in verilog modules (regs, wires, etc).
Other fixes, cleanups:
xls::verilog::SanitizeIdentifier renamed to SanitizeVerilogIdentifier to distinguish it from other uses of sanitize.
SanitizeVerilogIdentifier now sanitizes keywords.
Raise an error if port names collide rather than silently renaming because port names are part of the interface and should not be changed.
Don't call SanitizeVerilogIdentifer during block creation. We have a separate pass which handes that (NameLeagalizationPass).
Fixes #2209.
Fixes #805