list_cpu_features.exe does not detect SSE42 on Xeon X5650 (Windows)

[RainbowMiner]

Here is the documentation of that specific CPU:
https://ark.intel.com/content/www/us/en/ark/products/47922/intel-xeon-processor-x5650-12m-cache-2-66-ghz-6-40-gts-intel-qpi.html

Here is the output of list_cpu_features.exe:

arch            : x86
brand           : Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz
family          :   6 (0x06)
model           :  44 (0x2C)
stepping        :   2 (0x02)
uarch           : INTEL_WSM
flags           : aes,clfsh,cx16,cx8,dca,fpu,mmx,pclmulqdq,popcnt,smx,ss,sse,sse2,sse3,tsc
cache_info      : {"level":1,"cache_type":"data","cache_size":32768,"ways":8,"line_size":64,"tlb_entries":64,"partitioning":1},{"level":1,"cache_type":"instruction","cache_size":32768,"ways":4,"line_size":64,"tlb_entries":128,"partitioning":1},{"level":2,"cache_type":"unified","cache_size":262144,"ways":8,"line_size":64,"tlb_entries":512,"partitioning":1},{"level":3,"cache_type":"unified","cache_size":12582912,"ways":16,"line_size":64,"tlb_entries":12288,"partitioning":1}

If booted into Linux, sse4_2 is found. Partial output from cat /proc/cpuinfo:

processor       : 23
vendor_id       : GenuineIntel
cpu family      : 6
model           : 44
model name      : Intel(R) Xeon(R) CPU           X5650  @ 2.67GHz
stepping        : 2
microcode       : 0x1f
cpu MHz         : 2925.936
cache size      : 12288 KB
physical id     : 0
siblings        : 12
core id         : 10
cpu cores       : 6
apicid          : 21
initial apicid  : 21
fpu             : yes
fpu_exception   : yes
cpuid level     : 11
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2 popcnt aes lahf_lm pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid dtherm ida arat flush_l1d
bugs            : cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapgs itlb_multihit
bogomips        : 5319.94
clflush size    : 64
cache_alignment : 64
address sizes   : 40 bits physical, 48 bits virtual
power management:
...

[toor1245]

Hi @RainbowMiner, It is related to #4

[toor1245]

@gchatelet, @Mizux I see that all processors with uarch Westmere (Server) and Core EX has sse4, can we provide detection for Family 6 Model 47?

products-formerly-westmere-ex

Almost all processors with uarch Westmere (Server) and Core EP/Gulftown (Family 6 Model 44) support sse4 except (not specified in the docs):
intel-xeon-processor-l5638-12m-cache-2-00-ghz-5-86-gts-intel-qpi
intel-xeon-processor-l5618-12m-cache-1-87-ghz-5-86-gts-intel-qpi

products-formerly-westmere-ep

[gchatelet]

@RainbowMiner can you run cpuid -r -1 under linux and paste the result here so we can investigate further (and add the corresponding tests). I think we are indeed falling through the cracks of #4 (comment).

[gchatelet]

A gentle ping @RainbowMiner.

[toor1245]

@gchatelet, the same behaviour
PNG: http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00206F2_Eagleton_CPUID.png
CPUID Dump: http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00206F2_Eagleton_CPUID.txt

[gchatelet]

@toor1245

According to the wikipedia page, I think it's safe to enable MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 for all Westmere CPUs. What do you think?

[toor1245]

@gchatelet, yes, I agree with you, but we need to improve the OS support logic for Windows, according to the Intel docs:

Note: It is unwise for an application to rely exclusively on CPUID.1:ECX.AVX[bit 28] or at all on
CPUID.1:ECX.XSAVE[bit 26]: These indicate hardware support but not operating system support. If YMM
state management is not enabled by an operating systems, AVX instructions will #UD regardless of
CPUID.1:ECX.AVX[bit 28]. “CPUID.1:ECX.XSAVE[bit 26] = 1” does not guarantee the OS actually uses
the XSAVE process for state management.

So, we need to determine which version of Windows supports the instruction set.
See: Update WINVER and _WIN32_WINNT

it would also be nice if we also processed this case:
PF_XMMI64_INSTRUCTIONS_AVAILABLE - The SSE2 instruction set is available. Windows 2000: This feature is not supported.,
PF_SSE3_INSTRUCTIONS_AVAILABLE - Windows Server 2003 and Windows XP/2000: This feature is not supported.
https://docs.microsoft.com/en-us/windows/win32/api/processthreadsapi/nf-processthreadsapi-isprocessorfeaturepresent
https://docs.microsoft.com/en-us/windows-hardware/drivers/ddi/wdm/nf-wdm-exisprocessorfeaturepresent

[gchatelet]

Comment in #213 wrongly closed this issue.