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Merge tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.co…
…m/BayLibre/clk-meson into v4.18/dt64 First round of binding update for meson clocks targeted at v4.18 # gpg: Signature made Wed May 16 01:23:15 2018 PDT # gpg: using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85 # gpg: Can't check signature: No public key * tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson: dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks dt-bindings: clock: meson8b: export the NAND clock
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ | ||
/* | ||
* Copyright (c) 2016 BayLibre, SAS | ||
* Author: Neil Armstrong <narmstrong@baylibre.com> | ||
* | ||
* Copyright (c) 2018 Amlogic, inc. | ||
* Author: Qiufang Dai <qiufang.dai@amlogic.com> | ||
*/ | ||
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#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK | ||
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK | ||
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#define CLKID_AO_REMOTE 0 | ||
#define CLKID_AO_I2C_MASTER 1 | ||
#define CLKID_AO_I2C_SLAVE 2 | ||
#define CLKID_AO_UART1 3 | ||
#define CLKID_AO_UART2 4 | ||
#define CLKID_AO_IR_BLASTER 5 | ||
#define CLKID_AO_SAR_ADC 6 | ||
#define CLKID_AO_CLK81 7 | ||
#define CLKID_AO_SAR_ADC_SEL 8 | ||
#define CLKID_AO_SAR_ADC_DIV 9 | ||
#define CLKID_AO_SAR_ADC_CLK 10 | ||
#define CLKID_AO_ALT_XTAL 11 | ||
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#endif |
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ | ||
/* | ||
* Copyright (c) 2016 BayLibre, SAS | ||
* Author: Neil Armstrong <narmstrong@baylibre.com> | ||
* | ||
* Copyright (c) 2018 Amlogic, inc. | ||
* Author: Qiufang Dai <qiufang.dai@amlogic.com> | ||
*/ | ||
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#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK | ||
#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK | ||
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#define RESET_AO_REMOTE 0 | ||
#define RESET_AO_I2C_MASTER 1 | ||
#define RESET_AO_I2C_SLAVE 2 | ||
#define RESET_AO_UART1 3 | ||
#define RESET_AO_UART2 4 | ||
#define RESET_AO_IR_BLASTER 5 | ||
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#endif |