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Update README.md
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@gmlarumbe
gmlarumbe authored Aug 9, 2023
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Expand Up @@ -306,7 +306,7 @@ Create basic testbench environment from DUT file:

UVM Agent template:

<img src="https://github.com/gmlarumbe/verilog-ext/assets/51021955/3f22e657-abcf-4a79-ac0f-a3c5a922f9ef" width=400 height=300>
<img src="https://github.com/gmlarumbe/verilog-ext/assets/51021955/255e4b4b-afb7-4720-8b21-55796ae887eb" width=400 height=300>

Functions:

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