Update indent tests with indent-tabs-mode disabled

test/ref/indent/indent_4.v

@@ -1,22 +1,22 @@
 module foo;
     initial
-	begin
-	    s1;
-	end
+        begin
+            s1;
+        end
 
     always @(a)
-	begin
-	    s1;
-	end // always @ (a)
+        begin
+            s1;
+        end // always @ (a)
     always
-	begin
-	    s1;
-	end // always begin
+        begin
+            s1;
+        end // always begin
     always_ff
-	begin
-	end // always_ff begin
+        begin
+        end // always_ff begin
     task
-	t;
+        t;
     endtask // t
 
 endmodule // foo

test/ref/indent/indent_always_decl.v

@@ -3,32 +3,32 @@ module foo ();
     // indents to here: (which I like)
     //          V
     wire [10:0] mux_output0 =
-		select0[0] ? mux_input0 :
-		select0[1] ? mux_input1 :
-		select0[2] ? mux_input2 :
-		select0[3] ? mux_input3 :
-		select0[4] ? mux_input4 :
-		select0[5] ? mux_input5 :
-		select0[6] ? mux_input6 :
-		mux_input7;
+                select0[0] ? mux_input0 :
+                select0[1] ? mux_input1 :
+                select0[2] ? mux_input2 :
+                select0[3] ? mux_input3 :
+                select0[4] ? mux_input4 :
+                select0[5] ? mux_input5 :
+                select0[6] ? mux_input6 :
+                mux_input7;
 
     reg         foobar;
     always @(posedge clk)
-	if (reset_n) begin
-	    foobar <= 1'b0;
-	end
+        if (reset_n) begin
+            foobar <= 1'b0;
+        end
 
     // After the always block,
     // indents to here:
     //                       V
     wire [10:0] mux_output1 =
-		select1[0] ? mux_input8 :
-		select1[1] ? mux_input9 :
-		select1[2] ? mux_input10 :
-		select1[3] ? mux_input11 :
-		select1[4] ? mux_input12 :
-		select1[5] ? mux_input13 :
-		select1[6] ? mux_input14 :
-		mux_input15;
+                select1[0] ? mux_input8 :
+                select1[1] ? mux_input9 :
+                select1[2] ? mux_input10 :
+                select1[3] ? mux_input11 :
+                select1[4] ? mux_input12 :
+                select1[5] ? mux_input13 :
+                select1[6] ? mux_input14 :
+                mux_input15;
 endmodule
 

test/ref/indent/indent_analog.v

@@ -3,6 +3,6 @@ module mymodule();
     parameter real fc=10e6;
     parameter real bw=25e3;
     analog begin
-	// contents of module here
+        // contents of module here
     end
 endmodule

test/ref/indent/indent_assert.v

@@ -1,7 +1,7 @@
 module assert_test;
     reg [31:0] whatever2;
     initial begin
-	a = b;
-	assert(std::randomize(whatever2)  with { whatever2   inside {[10:100]};});
+        a = b;
+        assert(std::randomize(whatever2)  with { whatever2   inside {[10:100]};});
     end
 endmodule // assert_test

test/ref/indent/indent_assert_else.v

@@ -1,56 +1,56 @@
 module myassert(input clk,
-		input        reset,
-		input [15:0] data);
+                input        reset,
+                input [15:0] data);
 
     property myproperty;
-	@(posedge clk)
-	    $rose(reset) |-> data  == 16'h0;
+        @(posedge clk)
+            $rose(reset) |-> data  == 16'h0;
     endproperty
 
     //Assert, cover, and assume property statements
     //support begin/end keywords.  The else begin/end
     //clause below is getting indented improperly.
     myassert0: assert property(myproperty) begin
-	$display("myassert0 was successful");
-	a;
-	b;
-	c;
-	d;
+        $display("myassert0 was successful");
+        a;
+        b;
+        c;
+        d;
     end // myassert0: assert property (myproperty)
     else begin
-	$fatal("myassert0 was unsuccessful");
+        $fatal("myassert0 was unsuccessful");
     end // else: !assert property(myproperty)
     if (a) begin
-	b;
-	c;
+        b;
+        c;
     end // if (a)
     else begin
-	o;
+        o;
     end // else: !if(a)
 
     // TS: Add procedural block for non-concurrent assertion
     always @(posedge clk) begin
-	assert (a) begin
-	    o;
-	end // assert (a)
-	else begin
-	    o;
-	end // else: !assert (a)
+        assert (a) begin
+            o;
+        end // assert (a)
+        else begin
+            o;
+        end // else: !assert (a)
 
-	assert (statement) begin
-	    $display("assertion passed"); //this code is correctly indented
-	end // assert (statement)
-	else begin // this whole section should be moved to the left
-	    $error("assertion failed");
-	end // else: !assert (statement)
+        assert (statement) begin
+            $display("assertion passed"); //this code is correctly indented
+        end // assert (statement)
+        else begin // this whole section should be moved to the left
+            $error("assertion failed");
+        end // else: !assert (statement)
 
-	// TS: Add procedural block for non-concurrent assertion
+        // TS: Add procedural block for non-concurrent assertion
     end
 
     //Also, any statements following the assert,
     //cover, and assume property statements get
     // indented too far to the right.
     always @(posedge clk) begin
-	a;
+        a;
     end // always @ (posedge clk)
 endmodule

test/ref/indent/indent_assert_property.v

@@ -1,20 +1,20 @@
 module myassert(input clk,
-		input reset,
-		input [15:0] data);
+                input reset,
+                input [15:0] data);
 
     property myproperty;
-	@(posedge clk)
-	    $rose(reset) |-> data == 16'h0;
+        @(posedge clk)
+            $rose(reset) |-> data == 16'h0;
     endproperty
 
     //Assert, cover, and assume property statements
     //support begin/end keywords.  The else begin/end
     //clause below is getting indented improperly.
     myassert0: assert property(myproperty) begin
-	$display("myassert0 was successful");
+        $display("myassert0 was successful");
     end
     else begin
-	$fatal("myassert0 was unsuccessful");
+        $fatal("myassert0 was unsuccessful");
     end
 
     //Also, any statements following the assert,

test/ref/indent/indent_assignment.v

@@ -1,36 +1,36 @@
 // Issue 941 : The following operators should not be broken by auto-indents
 module m;
     initial begin
-	a = b;
-	a <= b;
-	a <<= b;
-	a <<<= b;
-	a >= b;
-	a >>= b;
-	a >>>= b;
-	a == b;
-	a != b;
-	a === b;
-	a !== b;
-	a ==? b;
-	a !=? b;
-	a <-> b;
-	a -> b;
-	a ->> b;
-	a |-> b;
-	a |=> b;
-	a #-# b;
-	a #=# b;
-	a := b;
-	a :/ b;
+        a = b;
+        a <= b;
+        a <<= b;
+        a <<<= b;
+        a >= b;
+        a >>= b;
+        a >>>= b;
+        a == b;
+        a != b;
+        a === b;
+        a !== b;
+        a ==? b;
+        a !=? b;
+        a <-> b;
+        a -> b;
+        a ->> b;
+        a |-> b;
+        a |=> b;
+        a #-# b;
+        a #=# b;
+        a := b;
+        a :/ b;
     end
 
     // bug1169
     assign a = t ?
-	       m :
-	       n;
+               m :
+               n;
     assign a = z ?
-	       m :
-	       n;
+               m :
+               n;
 
 endmodule

test/ref/indent/indent_begin_clapp.v

@@ -2,40 +2,40 @@
 module x;
 
     always @*
-	begin
-	end
+        begin
+        end
 
     initial
-	begin
-	end
+        begin
+        end
 
     final
-	begin
-	end
+        begin
+        end
 
     initial forever
-	begin
-	end
+        begin
+        end
 
     foreach(1)
-	begin
-	end
+        begin
+        end
 
     do
-	begin
-	end while (i);
+        begin
+        end while (i);
 
     initial @a.b
-	begin
-	end
+        begin
+        end
 
     always @E
-	begin
-	end
+        begin
+        end
 
     forever @E
-	begin
-	end
+        begin
+        end
 
 endmodule
 

test/ref/indent/indent_bracket.v

@@ -7,6 +7,6 @@ module foo
      output        ctl_out);
 
     assign data_out  = data_in[1] ? data_in[63:0]
-		       :            64'h0;
+                       :            64'h0;
 
 endmodule