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Update tags collection for tree-sitter-systemverilog grammar
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@gmlarumbe
gmlarumbe committed Aug 30, 2024
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2 changes: 1 addition & 1 deletion test-hdl
Submodule test-hdl updated 74 files
+38 −38 verilog/files/beautify/verilog-ext/ref/axi_demux.ts.sv
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+38 −38 verilog/files/indent/verilog-ts-mode/ref/axi_demux.sv
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+45 −45 verilog/files/indent/verilog-ts-mode/ref/uvm_component.svh
+1 −1 verilog/files/navigation/verilog-ext/ref/axi_test.ts.tf.bwd.el
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+12 −0 verilog/files/tags/verilog-ext/ref/axi_demux.ts.refs.el
+38 −18 verilog/files/tags/verilog-ext/ref/axi_test.ts.defs.el
+234 −34 verilog/files/tags/verilog-ext/ref/axi_test.ts.refs.el
+20 −0 verilog/files/tags/verilog-ext/ref/tb_program.ts.refs.el
+42 −0 verilog/files/tags/verilog-ext/ref/uvm_component.ts.refs.el
+1 −1 verilog/files/utils/verilog-ext/ref/instances.ts.block.at.point.el
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+3 −3 verilog/scripts/install-ts-grammar.sh
+1 −1 vhdl/files/tags/vhdl-ext/ref/axi_if_converter.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/axi_if_converter.ts.refs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/global_pkg.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/global_pkg.ts.refs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/global_sim.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/global_sim.ts.refs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/hierarchy.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/hierarchy.ts.refs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/indent_misc.ts.defs.el
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+1 −1 vhdl/files/tags/vhdl-ext/ref/instances.ts.defs.el
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+1 −1 vhdl/files/tags/vhdl-ext/ref/sexp.ts.defs.el
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+1 −1 vhdl/files/tags/vhdl-ext/ref/std_logic_1164-body.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/std_logic_1164-body.ts.refs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/std_logic_1164.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/std_logic_1164.ts.refs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/tb_axi_if_converter.ts.defs.el
+1 −1 vhdl/files/tags/vhdl-ext/ref/tb_axi_if_converter.ts.refs.el
40 changes: 33 additions & 7 deletions verilog-ext-tags.el
View file
Original file line number Diff line number Diff line change
Expand Up @@ -384,7 +384,7 @@ temp-buffer."
"constraint_declaration"
;; Ports/arguments
"ansi_port_declaration"
"tf_port_item1"
"tf_port_item"
;; Variable/net/parameter/type declarations
"variable_decl_assignment"
"net_decl_assignment"
Expand All @@ -397,7 +397,11 @@ temp-buffer."
"enum_name_declaration"
;; Instances
"module_instantiation"
"interface_instantiation")
"interface_instantiation"
"program_instantiation"
"checker_instantiation"
"gate_instantiation"
"udp_instantiation")
'symbols))
"Regexp of tree-sitter node types to be used for tags definitions.
Expand All @@ -417,7 +421,28 @@ completion.")

(defconst verilog-ext-tags-method-declaration-ts-re
(eval-when-compile
(regexp-opt '("task_declaration" "function_declaration" "class_constructor_declaration") 'symbols)))
(regexp-opt
'("task_declaration"
"function_declaration"
"class_constructor_declaration")
'symbols)))

(defconst verilog-ext-tags-ts-ref-nodes-re
(eval-when-compile
(regexp-opt
'("simple_identifier"
"system_tf_identifier"
"escaped_identifier"
"array_method_name"
"string_method_name"
"enum_method_name"
"associative_array_method_name"
"queue_method_name"
"array_or_queue_method_name"
"enum_or_associative_array_method_name"
"new")
'symbols)))


(defun verilog-ext-tags-table-push-defs-ts (file)
"Push current FILE definitions using tree-sitter.
Expand All @@ -442,9 +467,10 @@ TS-TYPE is provided to avoid an additional call to `treesit-node-type' since
this function is synctactic sugar for
`verilog-ext-tags-table-push-defs-ts--recurse'."
(cond (;; Externally defined methods
(and (string-match verilog-ext-tags-method-declaration-ts-re ts-type)
(verilog-ts--node-has-child-recursive ts-node "class_type"))
(verilog-ts--node-identifier-name (verilog-ts--node-has-child-recursive ts-node "class_identifier")))
(let (class-type-node)
(and (string-match verilog-ext-tags-method-declaration-ts-re ts-type)
(setq class-type-node (verilog-ts--node-has-child-recursive ts-node "class_type")))
(verilog-ts--node-identifier-name class-type-node)))
(t ;; Default
(verilog-ts--node-identifier-name parent-node))))

Expand Down Expand Up @@ -491,7 +517,7 @@ PARENT is passed as an argument to build the :items prop list of
Update hash table `verilog-ext-tags-refs-current-file'."
(let (tag pos line)
(dolist (node (verilog-ts-nodes "simple_identifier"))
(dolist (node (verilog-ts-nodes verilog-ext-tags-ts-ref-nodes-re))
(setq tag (treesit-node-text node :no-prop))
(setq pos (treesit-node-start node))
(setq line (line-number-at-pos pos))
Expand Down

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