Pinned Loading

1. sdram_controller_generator sdram_controller_generator Public

   A Chisel hardware generator for SDRAM controllers from their datasheets

   Scala 1

2. sorting_accelerator sorting_accelerator Public

   An open-source hardware accelerator for sorting large arrays

   Verilog 3 1

3. snn-practice snn-practice Public

   Practice implementing an SNN on FPGA

   SystemVerilog 1

4. ice40-uart-alu ice40-uart-alu Public

   Assignment for Winter 2025 - CSE 293 (Verilog to Silicon)

   SystemVerilog 1 2

5. tt09-clb tt09-clb Public

   Forked from TinyTapeout/tt09-verilog-template

   Tiny Tapeout 9 - Configurable Logic Block

   Python

6. HydroConnect HydroConnect Public

   Forked from YuMe-02/Hydroconnect

   HydroConnect - Water sensors in places where you actually need them!

   Swift