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ASoC: fsl_asrc: refine the setting of internal clock divider
The output divider should align with the output sample rate, if use ideal sample rate, there will be a lot of overload, which would cause underrun. The maximum divider of asrc clock is 1024, but there is no judgement for this limitation in driver, which may cause the divider setting not correct. For non-ideal ratio mode, the clock rate should divide the sample rate with no remainder, and the quotient should be less than 1024. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/23c634e4bf58afce5b3ae67f5f42e8d1cae2639a.1572252307.git.shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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