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Konstantin edited this page May 12, 2018
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- Homepage: http://www.clifford.at/yosys/
- Github: https://github.com/YosysHQ/yosys
- Reddit: https://www.reddit.com/r/yosys/
- to Strogonov Andrey, author of Strogonov A., Gorodkov P. "Verilog project implementation in the basis of Intel FPGA using Yosys synthesis tool" article (in russian)