Fill in CGB register holes in the Memory_Map page #603
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I was implementing BESS support and needed a quick reference for which registers are mapped or unmapped, DMG+ or CGB+, and so on. And luckily the specification called out KEY0 explicitly or I would have missed these four registers. I'm adding them to the main MMIO table for that reason, as I believe it should be reliable for the use case of quickly determining used and unused addresses. I did not include undocumented CGB registers because they can be treated as though they are unused. I also did not add a documentation section for KEY0 even though it stands out as not having a link. If someone were to write up a description of that register they could come back and wire up the link here. In the meantime it would also be reasonable to link the whole box to KEY1, link to the CGB registers page, or link to the relevant section of the Power Up Sequence page. Whichever you feel is most appropriate.
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I was implementing BESS support and needed a quick reference for which registers are mapped or unmapped, DMG+ or CGB+, and so on. And luckily the specification called out KEY0 explicitly or I would have missed these four registers.
I'm adding them to the main MMIO table for that reason, as I believe it should be reliable for the use case of quickly determining used and unused addresses.
I did not include undocumented CGB registers because they can be treated as though they are unused.
I also did not add a documentation section for KEY0 even though it stands out as not having a link. If someone were to write up a description of that register they could come back and wire up the link here.
In the meantime it would also be reasonable to link the whole box to KEY1, link to the CGB registers page, or link to the relevant section of the Power Up Sequence page. Whichever you feel is most appropriate.