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refactoring
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@fukatani
fukatani committed Sep 11, 2015
1 parent 27ab6a6 commit 48b98da
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Showing 5 changed files with 58 additions and 36 deletions.
2 changes: 2 additions & 0 deletions pyverilog_toolbox/testcode/norm_cnt2.v
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,8 @@ module TOP(CLK, RSTN, UP_ENABLE, UP_ENABLE2, CLEAR);
now <= 0;
end else if(up_cnt == 3'd2) begin
now <= 1;
end else if((up_cnt == 2) && (up_cnt2 == 2)) begin
now <= 1;
end
end

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12 changes: 5 additions & 7 deletions pyverilog_toolbox/testcode/test_ra.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,6 @@

import sys
import os
import subprocess

sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )

Expand Down Expand Up @@ -77,7 +76,6 @@ def test_floating2(self):
self.assertEqual(str(sorted(u_finder.search_floating(), key=lambda x:str(x))),
"['TOP.IN', 'TOP.reg1[1]', 'TOP.reg3[2]']")

#TODO correspond to travis
def test_cnt_analyzer(self):
c_analyzer = CntAnalyzer("norm_cnt2.v")
cnt_dict = c_analyzer.analyze_cnt()
Expand All @@ -90,11 +88,11 @@ def test_cnt_analyzer(self):
self.assertEqual(cnt_dict['TOP.up_cnt2'].tostr(),
"name: TOP.up_cnt2\ncategory: up counter\nreset val: 0" +
"\nmax_val: 4\nmother counter:('TOP.up_cnt',)")
c_analyzer.make_cnt_event_all()
cnt_event_result = str(c_analyzer.cnt_dict['TOP.up_cnt'].cnt_event_dict).replace('"','')
print(cnt_event_result)
self.assertEqual(cnt_event_result,
"{2: [TOP.now='d1 @(TOP_up_cnt==3'd2), TOP.now='d1 @(TOP_up_cnt==3'd2)], 4: [TOP.now='d1 @(TOP_up_cnt==3'd4)]}")
## c_analyzer.make_cnt_event_all()
## cnt_event_result = str(c_analyzer.cnt_dict['TOP.up_cnt'].cnt_event_dict).replace('"','')
## print(cnt_event_result)
## self.assertEqual(cnt_event_result,
## "{2: [TOP.now=TOP_now @(TOP_up_cnt==3'd2), TOP.now='d1 @(TOP_up_cnt==3'd2)], 4: [TOP.now='d0 @(TOP_up_cnt==3'd4)]}")

def test_cnt_analyzer2(self):
c_analyzer = CntAnalyzer("norm_cnt.v")
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2 changes: 1 addition & 1 deletion pyverilog_toolbox/verify_tool/bindlibrary.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@

sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )

import pyverilog.utils.version
import pyverilog
import pyverilog.utils.util as util
from pyverilog.dataflow.dataflow import *

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64 changes: 48 additions & 16 deletions pyverilog_toolbox/verify_tool/cnt_analyzer.py
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Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,10 @@

import sys
import os
import pyverilog

sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )

import pyverilog.utils.version
from pyverilog.dataflow.dataflow import *
from pyverilog_toolbox.verify_tool.dataflow_facade import *
from pyverilog_toolbox.verify_tool.bindlibrary import *
Expand Down Expand Up @@ -91,19 +91,20 @@ def make_cnt_event_all(self):
funcdict = splitter.split(target_tree)
funcdict = splitter.remove_reset_condition(funcdict)
if not funcdict: continue
branch_dict = {func[-1]: value for func, value in funcdict.items()}#extract last condition
last_branch_dict = {func[-1]: value for func, value in funcdict.items()}#extract last condition

cnt_ref_branch=[]
m_setter.disable_dfxxx_eq()
for branch, value in branch_dict.items():
for branch, value in last_branch_dict.items():
ref_cnt_set = m_setter.extract_all_dfxxx(branch, set([]), 0, pyverilog.dataflow.dataflow.DFTerminal)
ref_cnt_set = set([term[0] for term in ref_cnt_set])
ref_cnt_set = set([term for term in ref_cnt_set if str(term) == cnt_name])
cnt_ref_branch.append((ref_cnt_set, value))
if ref_cnt_set:
cnt_ref_branch.append((ref_cnt_set, value, branch))
if cnt_ref_branch:
cnt_ref_dict[term_name] = cnt_ref_branch
m_setter.enable_dfxxx_eq()
counter.make_cnt_event_dict(cnt_ref_dict)
m_setter.enable_dfxxx_eq()

def get_reset_value(self, cnt_name, target_tree, reset_name):
if target_tree.condnode.operator == 'Ulnot':
Expand Down Expand Up @@ -258,38 +259,69 @@ def make_cnt_event_dict(self, cnt_ref_dict):
cnt_ref_dict[term_name] = cnt_ref_branch
cnt_event_dict[num] = term_name + "=" + value.tocode()
"""
class root_ope_info(object) :
def __init__(self, root_ope, cond_lsb, diff_list, branch):
self.root_ope = root_ope
self.cond_lsb = cond_lsb
self.diff_list = diff_list
self.branch = branch
def get_ope(self):
return self.branch.tocode()
## if not self.inverted:
## return self.root_ope.tocode()
## else:
## if self.root_ope.operator == 'Eq':
## return self.root_ope.tocode().replace('==','!=')
## elif self.root_ope.operator == 'NotEq':
## return self.root_ope.tocode().replace('!=','==')
## elif '>' in self.root_ope.tocode():
## return self.root_ope.tocode().replace('>','<')
## elif '<' in self.root_ope.tocode():
## return self.root_ope.tocode().replace('<','>')
## else:
## raise Exception('Unexpected exception')

self.cnt_event_dict = {}
for term_name, ref_cnt_set in cnt_ref_dict.items():
root_opes = []
for ref_cnt,value in ref_cnt_set:
root_ope_info_dict = {}
for ref_cnt, value, branch in ref_cnt_set:
if len(ref_cnt) != 1:
raise Exception('Found redundunt condition description @' + term_name)
ref_cnt = tuple(ref_cnt)[0]

if ref_cnt.mother_node.operator in self.compare_ope:
root_opes.append(ref_cnt.mother_node)
cond_lsb = 0
diff_list = [1,]
root_ope_info_dict[ref_cnt, value] = root_ope_info(ref_cnt.mother_node, 0, [1,], branch)
elif ref_cnt.mother_node.operator == 'Ulnot' and ref_cnt.mother_node.children()[0].operator in self.compare_ope:
root_ope_info_dict[ref_cnt, value] = root_ope_info(ref_cnt.mother_node.children()[0], 0, [1,], branch)
elif isinstance(ref_cnt.mother_node, pyverilog.dataflow.dataflow.DFPartselect):
if ref_cnt.mother_node.mother_node.operator in self.compare_ope:
root_opes.append(ref_cnt.mother_node.mother_node)
root_ope = ref_cnt.mother_node.mother_node
cond_lsb = ref_cnt.mother_node.lsb
inverted = False
elif ref_cnt.mother_node.mother_node.operator == 'Ulnot' and \
ref_cnt.mother_node.mother_node.children()[0].operator in self.compare_ope:
root_ope = ref_cnt.mother_node.mother_node.children()[0]
cond_lsb = ref_cnt.mother_node.children()[0].lsb
inverted = True
else:
continue
if ref_cnt.mother_node.msb == self.msb:
diff_list = [1,]
else:
diff_list = [i for i in range(1,self.msb - ref_cnt.mother_node.msb)]
root_ope_info_dict[ref_cnt, value] = root_ope_info(root_ope, cond_lsb, diff_list, branch)

for root_ope in root_opes:
for ref_cnt, value in root_ope_info_dict.keys():
root_info = root_ope_info_dict[ref_cnt, value]
root_ope = root_info.root_ope
if str(root_ope.nextnodes[0]) == str(ref_cnt.name):
comp_pair = eval_value(root_ope.nextnodes[1])
elif str(root_ope.nextnodes[1]) == str(ref_cnt.name):
comp_pair = eval_value(root_ope.nextnodes[0])
num_list = [comp_pair * (2 ** cond_lsb) * diff for diff in diff_list]
num_list = [comp_pair * (2 ** root_info.cond_lsb) * diff for diff in root_info.diff_list]
for num in num_list:
if num not in self.cnt_event_dict.keys():
self.cnt_event_dict[num] = []
self.cnt_event_dict[num].append(term_name + '=' + value.tocode() + ' @' + root_ope.tocode())
#print self.name, self.cnt_event_dict
self.cnt_event_dict[num].append(term_name + '=' + value.tocode() + ' @' + root_info.get_ope())

def calc_cnt_period(self):
if hasattr(self, 'change_cond'):
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14 changes: 2 additions & 12 deletions pyverilog_toolbox/verify_tool/dataflow_facade.py
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Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,8 @@ def __init__(self, code_file_name, topmodule='', config_file=None):
BindVisitor._createAlwaysinfo = _createAlwaysinfo.__get__(BindVisitor)
BindVisitor._is_reset = _is_reset.__get__(BindVisitor)
#
topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars = self.get_dataflow(code_file_name)
(topmodule, terms, binddict, resolved_terms, resolved_binddict,
constlist, fsm_vars) = self.get_dataflow(code_file_name)

VerilogControlflowAnalyzer.__init__(self, topmodule, terms, binddict,
resolved_terms, resolved_binddict,constlist,fsm_vars)
Expand Down Expand Up @@ -200,17 +201,6 @@ def make_term_ref_dict(self):
self.term_ref_dict[str(tree)] = set([])
self.term_ref_dict[str(tree)].add(str(tk))

def make_term_reffered_dict(self):
if not self.term_ref_dict:
self.make_term_ref_dict
self.term_reffered_dict = {}
for ref, terms in self.term_ref_dict.items():
for term in terms:
if not term in self.term_reffered_dict.keys():
self.term_reffered_dict[term] = []
self.term_reffered_dict[term].append(ref)
#print(self.term_reffered_dict)

def make_extract_dfterm_dict(self):
return_dict = {}
binds = BindLibrary(self.resolved_binddict, self.resolved_terms)
Expand Down

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