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char: replace PROP_CHR with CharBackend
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Store the property in a CharBackend instead of CharDriverState*.  This
also replace systematically chr by chr.chr to access the
CharDriverState*. The following patches will replace it with calls to
qemu_chr_fe CharBackend functions.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20161022095318.17775-12-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@elmarco @bonzini
elmarco authored and bonzini committed Oct 24, 2016
1 parent ecb672d commit becdfa0
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Showing 37 changed files with 302 additions and 265 deletions.
18 changes: 10 additions & 8 deletions hw/arm/pxa2xx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1764,7 +1764,7 @@ struct PXA2xxFIrState {
qemu_irq rx_dma;
qemu_irq tx_dma;
uint32_t enable;
CharDriverState *chr;
CharBackend chr;

uint8_t control[3];
uint8_t status[2];
Expand Down Expand Up @@ -1898,14 +1898,16 @@ static void pxa2xx_fir_write(void *opaque, hwaddr addr,
pxa2xx_fir_update(s);
break;
case ICDR:
if (s->control[2] & (1 << 2)) /* TXP */
if (s->control[2] & (1 << 2)) { /* TXP */
ch = value;
else
} else {
ch = ~value;
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
}
if (s->chr.chr && s->enable && (s->control[0] & (1 << 3))) { /* TXE */
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &ch, 1);
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
}
break;
case ICSR0:
s->status[0] &= ~(value & 0x66);
Expand Down Expand Up @@ -1973,9 +1975,9 @@ static void pxa2xx_fir_realize(DeviceState *dev, Error **errp)
{
PXA2xxFIrState *s = PXA2XX_FIR(dev);

if (s->chr) {
qemu_chr_fe_claim_no_fail(s->chr);
qemu_chr_add_handlers(s->chr, pxa2xx_fir_is_empty,
if (s->chr.chr) {
qemu_chr_fe_claim_no_fail(s->chr.chr);
qemu_chr_add_handlers(s->chr.chr, pxa2xx_fir_is_empty,
pxa2xx_fir_rx, pxa2xx_fir_event, s);
}
}
Expand Down
14 changes: 7 additions & 7 deletions hw/arm/strongarm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -912,7 +912,7 @@ typedef struct StrongARMUARTState {
SysBusDevice parent_obj;

MemoryRegion iomem;
CharDriverState *chr;
CharBackend chr;
qemu_irq irq;

uint8_t utcr0;
Expand Down Expand Up @@ -1020,8 +1020,8 @@ static void strongarm_uart_update_parameters(StrongARMUARTState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
s->char_transmit_time = (NANOSECONDS_PER_SECOND / speed) * frame_size;
if (s->chr) {
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
if (s->chr.chr) {
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}

DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
Expand Down Expand Up @@ -1107,10 +1107,10 @@ static void strongarm_uart_tx(void *opaque)

if (s->utcr3 & UTCR3_LBM) /* loopback */ {
strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
} else if (s->chr) {
} else if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &s->tx_fifo[s->tx_start], 1);
qemu_chr_fe_write_all(s->chr.chr, &s->tx_fifo[s->tx_start], 1);
}

s->tx_start = (s->tx_start + 1) % 8;
Expand Down Expand Up @@ -1239,8 +1239,8 @@ static void strongarm_uart_init(Object *obj)
s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_rx_to, s);
s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);

if (s->chr) {
qemu_chr_add_handlers(s->chr,
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr,
strongarm_uart_can_receive,
strongarm_uart_receive,
strongarm_uart_event,
Expand Down
12 changes: 6 additions & 6 deletions hw/char/bcm2835_aux.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,8 @@ static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size)
s->read_pos = 0;
}
}
if (s->chr) {
qemu_chr_accept_input(s->chr);
if (s->chr.chr) {
qemu_chr_accept_input(s->chr.chr);
}
bcm2835_aux_update(s);
return c;
Expand Down Expand Up @@ -168,10 +168,10 @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value,
case AUX_MU_IO_REG:
/* "DLAB bit set means access baudrate register" is NYI */
ch = value;
if (s->chr) {
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &ch, 1);
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
}
break;

Expand Down Expand Up @@ -282,8 +282,8 @@ static void bcm2835_aux_realize(DeviceState *dev, Error **errp)
{
BCM2835AuxState *s = BCM2835_AUX(dev);

if (s->chr) {
qemu_chr_add_handlers(s->chr, bcm2835_aux_can_receive,
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, bcm2835_aux_can_receive,
bcm2835_aux_receive, NULL, s);
}
}
Expand Down
26 changes: 13 additions & 13 deletions hw/char/cadence_uart.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -142,8 +142,8 @@ static void uart_rx_reset(CadenceUARTState *s)
{
s->rx_wpos = 0;
s->rx_count = 0;
if (s->chr) {
qemu_chr_accept_input(s->chr);
if (s->chr.chr) {
qemu_chr_accept_input(s->chr.chr);
}
}

Expand All @@ -156,8 +156,8 @@ static void uart_send_breaks(CadenceUARTState *s)
{
int break_enabled = 1;

if (s->chr) {
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
if (s->chr.chr) {
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_BREAK,
&break_enabled);
}
}
Expand Down Expand Up @@ -210,8 +210,8 @@ static void uart_parameters_setup(CadenceUARTState *s)

packet_size += ssp.data_bits + ssp.stop_bits;
s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
if (s->chr) {
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
if (s->chr.chr) {
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}
}

Expand Down Expand Up @@ -278,7 +278,7 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
int ret;

/* instant drain the fifo when there's no back-end */
if (!s->chr) {
if (!s->chr.chr) {
s->tx_count = 0;
return FALSE;
}
Expand All @@ -287,15 +287,15 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
return FALSE;
}

ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);
ret = qemu_chr_fe_write(s->chr.chr, s->tx_fifo, s->tx_count);

if (ret >= 0) {
s->tx_count -= ret;
memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
}

if (s->tx_count) {
guint r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
guint r = qemu_chr_fe_add_watch(s->chr.chr, G_IO_OUT | G_IO_HUP,
cadence_uart_xmit, s);
if (!r) {
s->tx_count = 0;
Expand Down Expand Up @@ -368,8 +368,8 @@ static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
*c = s->rx_fifo[rx_rpos];
s->rx_count--;

if (s->chr) {
qemu_chr_accept_input(s->chr);
if (s->chr.chr) {
qemu_chr_accept_input(s->chr.chr);
}
} else {
*c = 0;
Expand Down Expand Up @@ -474,8 +474,8 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
fifo_trigger_update, s);

if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_receive, uart_receive,
uart_event, s);
}
}
Expand Down
8 changes: 4 additions & 4 deletions hw/char/debugcon.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@

typedef struct DebugconState {
MemoryRegion io;
CharDriverState *chr;
CharBackend chr;
uint32_t readback;
} DebugconState;

Expand All @@ -62,7 +62,7 @@ static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,

/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &ch, 1);
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
}


Expand All @@ -87,12 +87,12 @@ static const MemoryRegionOps debugcon_ops = {

static void debugcon_realize_core(DebugconState *s, Error **errp)
{
if (!s->chr) {
if (!s->chr.chr) {
error_setg(errp, "Can't create debugcon device, empty char device");
return;
}

qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);
qemu_chr_add_handlers(s->chr.chr, NULL, NULL, NULL, s);
}

static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
Expand Down
8 changes: 4 additions & 4 deletions hw/char/digic-uart.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -76,10 +76,10 @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,

switch (addr) {
case R_TX:
if (s->chr) {
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &ch, 1);
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
}
break;

Expand Down Expand Up @@ -147,8 +147,8 @@ static void digic_uart_realize(DeviceState *dev, Error **errp)
{
DigicUartState *s = DIGIC_UART(dev);

if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr, uart_can_rx, uart_rx, uart_event, s);
}
}

Expand Down
21 changes: 11 additions & 10 deletions hw/char/escc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ typedef struct ChannelState {
uint32_t reg;
uint8_t wregs[SERIAL_REGS], rregs[SERIAL_REGS];
SERIOQueue queue;
CharDriverState *chr;
CharBackend chr;
int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
int disabled;
int clock;
Expand Down Expand Up @@ -416,7 +416,7 @@ static void escc_update_parameters(ChannelState *s)
int speed, parity, data_bits, stop_bits;
QEMUSerialSetParams ssp;

if (!s->chr || s->type != ser)
if (!s->chr.chr || s->type != ser)
return;

if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
Expand Down Expand Up @@ -466,7 +466,7 @@ static void escc_update_parameters(ChannelState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;
trace_escc_update_parameters(CHN_C(s), speed, parity, data_bits, stop_bits);
qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}

static void escc_mem_write(void *opaque, hwaddr addr,
Expand Down Expand Up @@ -556,11 +556,11 @@ static void escc_mem_write(void *opaque, hwaddr addr,
trace_escc_mem_writeb_data(CHN_C(s), val);
s->tx = val;
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
if (s->chr)
if (s->chr.chr) {
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &s->tx, 1);
else if (s->type == kbd && !s->disabled) {
qemu_chr_fe_write_all(s->chr.chr, &s->tx, 1);
} else if (s->type == kbd && !s->disabled) {
handle_kbd_command(s, val);
}
}
Expand Down Expand Up @@ -599,8 +599,9 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr,
else
ret = s->rx;
trace_escc_mem_readb_data(CHN_C(s), ret);
if (s->chr)
qemu_chr_accept_input(s->chr);
if (s->chr.chr) {
qemu_chr_accept_input(s->chr.chr);
}
return ret;
default:
break;
Expand Down Expand Up @@ -1013,9 +1014,9 @@ static void escc_realize(DeviceState *dev, Error **errp)
ESCC_SIZE << s->it_shift);

for (i = 0; i < 2; i++) {
if (s->chn[i].chr) {
if (s->chn[i].chr.chr) {
s->chn[i].clock = s->frequency / 2;
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
qemu_chr_add_handlers(s->chn[i].chr.chr, serial_can_receive,
serial_receive1, serial_event, &s->chn[i]);
}
}
Expand Down
8 changes: 4 additions & 4 deletions hw/char/etraxfs_ser.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ typedef struct ETRAXSerial {
SysBusDevice parent_obj;

MemoryRegion mmio;
CharDriverState *chr;
CharBackend chr;
qemu_irq irq;

int pending_tx;
Expand Down Expand Up @@ -128,7 +128,7 @@ ser_write(void *opaque, hwaddr addr,
case RW_DOUT:
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &ch, 1);
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
s->regs[R_INTR] |= 3;
s->pending_tx = 1;
s->regs[addr] = value;
Expand Down Expand Up @@ -231,8 +231,8 @@ static void etraxfs_ser_realize(DeviceState *dev, Error **errp)
{
ETRAXSerial *s = ETRAX_SERIAL(dev);

if (s->chr) {
qemu_chr_add_handlers(s->chr,
if (s->chr.chr) {
qemu_chr_add_handlers(s->chr.chr,
serial_can_receive, serial_receive,
serial_event, s);
}
Expand Down
10 changes: 5 additions & 5 deletions hw/char/exynos4210_uart.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ typedef struct Exynos4210UartState {
Exynos4210UartFIFO rx;
Exynos4210UartFIFO tx;

CharDriverState *chr;
CharBackend chr;
qemu_irq irq;

uint32_t channel;
Expand Down Expand Up @@ -346,7 +346,7 @@ static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
ssp.data_bits = data_bits;
ssp.stop_bits = stop_bits;

qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
qemu_chr_fe_ioctl(s->chr.chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);

PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
s->channel, speed, parity, data_bits, stop_bits);
Expand Down Expand Up @@ -383,13 +383,13 @@ static void exynos4210_uart_write(void *opaque, hwaddr offset,
break;

case UTXH:
if (s->chr) {
if (s->chr.chr) {
s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
UTRSTAT_Tx_BUFFER_EMPTY);
ch = (uint8_t)val;
/* XXX this blocks entire thread. Rewrite to use
* qemu_chr_fe_write and background I/O callbacks */
qemu_chr_fe_write_all(s->chr, &ch, 1);
qemu_chr_fe_write_all(s->chr.chr, &ch, 1);
#if DEBUG_Tx_DATA
fprintf(stderr, "%c", ch);
#endif
Expand Down Expand Up @@ -640,7 +640,7 @@ static int exynos4210_uart_init(SysBusDevice *dev)

sysbus_init_irq(dev, &s->irq);

qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
qemu_chr_add_handlers(s->chr.chr, exynos4210_uart_can_receive,
exynos4210_uart_receive, exynos4210_uart_event, s);

return 0;
Expand Down
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