If you are here you are hopefully considering contributing some useful chisel modules to the community. This is the place to do it.
| Package | Type | Developer | Descpription |
|---|---|---|---|
| BitonicSorter | internal | Steve Burns | A combinational sort generator for arbitrarily typed Vectors |
| IterativeCordic | internal | Harrison Liew | An iterative Cordic implementation |
| aes_chisel | maven | Sergiu Mosanu | Implementation of the Advanced Encryption Standard (AES) How to get it |
| uart | internal | Martin Schoeberl | A basic serial port (UART) |
| fifo | internal | Martin Schoeberl | Variations of FIFO queues |
| spi2wb | maven | Fabien Marteau | Drive a wishbone master bus with SPI |
| dclib | internal | Guy Hutchison | Utility components for DecoupledIO interfaces |
| ecc | internal | Guy Hutchison | Hamming Error-Correcting code modules |
| iir | internal | Kevin Joly | Infinite Impulse Response filter module |
| fir | internal | Kevin Joly | Finite Impulse Response filter module |
ip-contributions is published with Maven central and to use it simply add following
line to your build.sbt
libraryDependencies += "edu.berkeley.cs" % "ip-contributions" % "5.3.0"
ip-contributions exists for different Chisel/Scala versions:
| ip-contributions | Chisel | Scala |
|---|---|---|
| 5.3.0 | 5.3.0 | 2.13 |
| 0.6.1 | 3.6.1 | 2.13 |
| 0.5.4 | 3.5.6 | 2.13 |
| 0.5.3 | 3.5.6 | 2.12 |
| 0.5.1 | 3.5.5 | 2.12 |
| 0.4.0 | 3.4.x | 2.12 |
To begin with you should have some working Chisel code. Adding it is designed to be as simple as possible. There are two main ways to go about this.
- Creating a new package here in the src/main/scala and src/test/scala and place your circuit and it's unit tests in those respective directories. More about this
- Create an external repository and distribute it via the Maven, let us review it and provides links to it.
- Developer Sergiu Mosanu
- Repository https://github.com/hplp/aes_chisel
- Versions 3.2, 3.1
- Sbt Dependency com.github.hplp" %% "aes_chisel" % "3.2.0"
aes_chisel's goals are to:
- Implement an open-source, transparent, secure encryption module in Chisel
- Equip developers with ready-to-use, efficient, parameterizable, encryption macros for RISC-V systems
- Compare performance and resource utilization of generated HDL with pure Verilog and Vivado HLS
- Compare code size with Verilog, Python, C++ and Vivado HLS as a index of development productivity
- Developer Fabien Marteau
- Repository https://github.com/Martoni/spi2wb
- Versions 1.3, 1.2, 1.1, 1.0
- Sbt Dependency com.github.hplp" %% "spi2wb" % "1.3"
spi2wb's goals are to:
- Drive a wishbone master bus with SPI
- Be easy to integrate in little FPGA
- Be used with simple computer and USB tools like BusPirate
- Avoid usage of softcore under the FPGA to drive wishbone peripherals
- Code Style should reasonably follow the default style guide used by the Chisel3 project. See the chisel3 scalastyle-config
- Unit Tests should be provided that reasonable confidence that a contribution works
- Useful README.md should be added in your package directory with contribution specific info.
- Licensing this code is still a WIP
This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or distribute this software, either in source code form or as a compiled binary, for any purpose, commercial or non-commercial, and by any means.
In jurisdictions that recognize copyright laws, the author or authors of this software dedicate any and all copyright interest in the software to the public domain. We make this dedication for the benefit of the public at large and to the detriment of our heirs and successors. We intend this dedication to be an overt act of relinquishment in perpetuity of all present and future rights to this software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to http://unlicense.org/