An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

Open source retro ISA video card

An attempt to recreate the RP2040 PIO in an FPGA

A simple, basic, formally verified UART controller

FPGA core boards / evaluation boards based on CDCTL hardware

ice40 USB Analyzer

Example Verilog code for Ulx3s

Quickstart guide on Icarus Verilog.

USB serial device (CDC-ACM)

Drop In USB CDC ACM core for iCE40 FPGA

Projects for building MIL-STD-1553 communications devices

include hdlc (miao), 422 grapher, 1553b

I2C ROM for EDID (Extended Display Identification Data) on FPGAs

UART To SPI

FPGA glitcher based on toothlessco's arty-glitcher, but for the icebreaker

Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.

Implemented The UART with FIFO

Behavioural design of UART with a FIFO buffer in verilog

BlackIce port of the Open Bench Logic Sniffer

An attempt to recreate the RP2040 PIO in an FPGA

Simple 8-bit port 80h listener for ISA bus with 7-segment display.

通过Python开发的一套根据verilog模块生成对应TOP、test_bench、connection信号等，并在不断优化中！

An attempt to recreate the RP2040 PIO in an FPGA

Your one-stop shop for all fpga programs- in your favourite language-->Python

A UART in Verilog

HDLC deframer can be used to convert framer to packets. The deframer modifies the bytes streams output of the framer to discrete packets, adding SOP and EOP. It also verifies the CRC over the packe…

This code is running on Cyclone IV E development board. Users are allowed to input the number that are going to send. The number will display on Nixie tube. Users can set the "wrong" lower frequenc…

Módulo bidireccional I2C

FPGA Based UART in Verilog

base uart pmod1553 project files without IP.