add riscv support

fix briansmith#1182
felixonmars · Sep 8, 2021 · cf3a51e · cf3a51e
1 parent 022f4db
commit cf3a51e
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diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -184,6 +184,8 @@ jobs:
           - x86_64-apple-darwin
           - x86_64-unknown-linux-musl
           - x86_64-unknown-linux-gnu
+          - riscv64gc-unknown-linux-gnu
+          - riscv32gc-unknown-linux-gnu
 
         mode:
           - # debug
@@ -259,6 +261,12 @@ jobs:
           - target: x86_64-unknown-linux-gnu
             host_os: ubuntu-18.04
 
+          - target: riscv64gc-unknown-linux-gnu
+            host_os: ubuntu-18.04
+
+          - target: riscv32gc-unknown-linux-gnu
+            host_os: ubuntu-18.04
+
     steps:
       - if: ${{ contains(matrix.host_os, 'ubuntu') }}
         run: sudo apt-get update -y

diff --git a/build.rs b/build.rs
@@ -200,6 +200,20 @@ const ASM_TARGETS: &[AsmTarget] = &[
         asm_extension: "S",
         preassemble: false,
     },
+    AsmTarget {
+        oss: LINUX_ABI,
+        arch: "riscv32",
+        perlasm_format: "linux32",
+        asm_extension: "S",
+        preassemble: false,
+    },
+    AsmTarget {
+        oss: LINUX_ABI,
+        arch: "riscv64",
+        perlasm_format: "linux64",
+        asm_extension: "S",
+        preassemble: false,
+    },
     AsmTarget {
         oss: MACOS_ABI,
         arch: "aarch64",

diff --git a/include/ring-core/base.h b/include/ring-core/base.h
@@ -91,6 +91,14 @@
 #define OPENSSL_MIPS64
 #elif defined(__wasm__)
 #define OPENSSL_32_BIT
+#elif defined(__riscv)
+# if (__riscv_xlen == 64)
+#  define OPENSSL_64_BIT
+#  define OPENSSL_RISCV64
+# elif(__riscv_xlen == 32)
+#  define OPENSSL_32_BIT
+#  define OPENSSL_RISCV32
+# endif
 #else
 // Note BoringSSL only supports standard 32-bit and 64-bit two's-complement,
 // little-endian architectures. Functions will not produce the correct answer