TLAST Signal Missing in IP Core Generated by HLS4ML

[SIRIDHARI]

Hi,
I am using Vitis HLS for my signature forgery detection project. I wrote the ML model in Python and used HLS4ML to convert it into C++ files. I then used Vitis HLS to generate RTL files.

I am planning to include DMA in my block design, so I need the TLAST signal. However, although I am using io_stream in HLS4ML (which should automatically generate the TLAST signal), it is not being generated in the RTL files.

Additionally, I am unsure where to connect the ap_ctrl signals generated in the IP core within the Vivado block design.

Has anyone faced a similar issue or knows how to ensure TLAST is included in the RTL design? Any help or suggestions would be greatly appreciated.