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[Xtensa] Implement CTLZ/CTTZ with NSAU (LLVM-277) #77

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[Xtensa] Implement CTLZ/CTTZ with NSAU (LLVM-277) #77

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22 changes: 18 additions & 4 deletions llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -198,10 +198,12 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTR, MVT::i32, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Expand);
if (Subtarget.hasNSA())
setOperationAction(ISD::CTLZ, MVT::i32, Legal);
else
setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Expand);


setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
Expand Down Expand Up @@ -389,6 +391,18 @@ bool XtensaTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
return false;
}

bool XtensaTargetLowering::isCheapToSpeculateCtlz(Type *) const {
return Subtarget.hasNSA();
}

bool XtensaTargetLowering::isCheapToSpeculateCttz(Type *) const {
return Subtarget.hasNSA();
}

bool XtensaTargetLowering::isCtlzFast() const {
return Subtarget.hasNSA();
}

/// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad.
Register XtensaTargetLowering::getExceptionPointerRegister(
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/Xtensa/XtensaISelLowering.h
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Expand Up @@ -120,6 +120,12 @@ class XtensaTargetLowering : public TargetLowering {
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
EVT VT) const override;

bool isCheapToSpeculateCtlz(Type *Ty) const override;

bool isCheapToSpeculateCttz(Type *Ty) const override;

bool isCtlzFast() const override;

/// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad.
Register
Expand Down
3 changes: 2 additions & 1 deletion llvm/lib/Target/Xtensa/XtensaInstrInfo.td
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Expand Up @@ -1346,7 +1346,8 @@ def NSA : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s),
}

def NSAU : RRR_Inst<0x00, 0x00, 0x04, (outs AR:$t), (ins AR:$s),
"nsau\t$t, $s", []>, Requires<[HasNSA]> {
"nsau\t$t, $s",
[(set AR:$t, (ctlz AR:$s))]>, Requires<[HasNSA]> {
let r = 0xF;
}

Expand Down
67 changes: 67 additions & 0 deletions llvm/test/CodeGen/Xtensa/ctlz-cttz.ll
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@@ -0,0 +1,67 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=xtensa -mcpu=esp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=XTENSA %s

declare i32 @llvm.ctlz.i32(i32, i1)

define i32 @test1_ctlz(i32 %v) {
; XTENSA-LABEL: test1_ctlz:
; XTENSA: # %bb.0:
; XTENSA-NEXT: entry a1, 32
; XTENSA-NEXT: .cfi_def_cfa_offset 32
; XTENSA-NEXT: nsau a2, a2
; XTENSA-NEXT: retw.n
%1 = tail call i32 @llvm.ctlz.i32(i32 %v, i1 false)
ret i32 %1
}

define i32 @test2_ctlz(i32 %v) {
; XTENSA-LABEL: test2_ctlz:
; XTENSA: # %bb.0:
; XTENSA-NEXT: entry a1, 32
; XTENSA-NEXT: .cfi_def_cfa_offset 32
; XTENSA-NEXT: nsau a2, a2
; XTENSA-NEXT: retw.n
%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}

declare i32 @llvm.cttz.i32(i32, i1)

define i32 @test1_cttz(i32 %v) {
; XTENSA-LABEL: test1_cttz:
; XTENSA: # %bb.0:
; XTENSA-NEXT: entry a1, 32
; XTENSA-NEXT: .cfi_def_cfa_offset 32
; XTENSA-NEXT: movi.n a8, -1
; XTENSA-NEXT: xor a8, a2, a8
; XTENSA-NEXT: addi.n a9, a2, -1
; XTENSA-NEXT: and a8, a8, a9
; XTENSA-NEXT: nsau a8, a8
; XTENSA-NEXT: movi.n a9, 32
; XTENSA-NEXT: sub a2, a9, a8
; XTENSA-NEXT: retw.n
%1 = tail call i32 @llvm.cttz.i32(i32 %v, i1 false)
ret i32 %1
}

define i32 @test2_cttz(i32 %v) {
; XTENSA-LABEL: test2_cttz:
; XTENSA: # %bb.0:
; XTENSA-NEXT: entry a1, 32
; XTENSA-NEXT: .cfi_def_cfa_offset 32
; XTENSA-NEXT: movi.n a8, -1
; XTENSA-NEXT: xor a8, a2, a8
; XTENSA-NEXT: addi.n a9, a2, -1
; XTENSA-NEXT: and a8, a8, a9
; XTENSA-NEXT: nsau a8, a8
; XTENSA-NEXT: movi.n a9, 32
; XTENSA-NEXT: sub a2, a9, a8
; XTENSA-NEXT: retw.n
%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
%tobool = icmp eq i32 %v, 0
%cond = select i1 %tobool, i32 32, i32 %cnt
ret i32 %cond
}
12 changes: 12 additions & 0 deletions llvm/test/MC/Xtensa/xtensa-valid-nsa.s
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@@ -0,0 +1,12 @@
# RUN: llvm-mc %s -triple=xtensa -mattr=+nsa -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s

# Instruction format RRR
# CHECK-INST: nsa a3, a2
# CHECK: encoding: [0x30,0xe2,0x40]
nsa a3, a2

# Instruction format RRR
# CHECK-INST: nsau a3, a2
# CHECK: encoding: [0x30,0xf2,0x40]
nsau a3, a2